STM32 Core Board PCB Design: Rules and Layer Planning
A microcontroller core board looks simple: one large device, a handful of passives and a connector that breaks out the pins. In practice it is one of the harder boards to lay out well, because the processor is fast, the power distribution network has to be effective across a wide frequency range, and the crystal and the analog supplies are sensitive to the switching activity happening a few millimetres away. The design rules below are drawn from the way a core board is actually built in production, and each of them exists because a board that ignored it failed a bring-up test.
Layer Planning Before Placement
A four-layer board is the minimum sensible choice for a modern microcontroller. The recommended arrangement places a ground plane directly beneath the component side, so that every signal on the top layer has an immediate reference, and a power plane beneath it, with the bottom layer used for routing where the density demands it.
A six-layer stack gives noticeably better behaviour and is worth the cost when the board includes external memory, a USB interface or an Ethernet PHY. The extra layers allow a dedicated ground beneath both signal layers and a split power plane that keeps the analog supply separated from the digital one. The general rules that govern those arrangements are set out in this article on layer stackup design, and they apply to a core board exactly as they apply to a larger system.
Decoupling and the Power Distribution Network
The decoupling network on a microcontroller is not a single capacitor placed nearby. It is a hierarchy. A bulk capacitor of a few microfarads handles the slower current demand, a mid-value capacitor of 100 nanofarads handles the mid-band, and one small capacitor per power pin handles the high-frequency transient generated when an output switches. The small capacitors must be as close to the pin as the layout allows, with a short and wide connection to the ground plane, because the inductance of that connection determines whether the capacitor does anything at all above a few tens of megahertz.
Placement order matters. The ground plane via should be adjacent to the capacitor pad so that the loop formed by the capacitor, the pin and the plane is minimal. Feeding the ground side of a decoupling capacitor through a long trace to a distant via destroys most of its value, even if the capacitor itself is a high-quality part.
The analog supply pins should be treated separately. They are usually fed through a ferrite bead or a small resistor from the digital rail, with their own decoupling, so that the switching noise on the digital supply does not reach the analog reference. If the device has a separate analog ground pin, it should be connected to the ground plane at a single defined point rather than being allowed to find its own path.
Crystal Layout
The crystal and its load capacitors form an oscillator whose frequency depends on the capacitance seen by the crystal, and that capacitance includes the parasitic capacitance of the traces. This makes the crystal layout a controlled-impedance problem in miniature: the traces between the device pins and the crystal should be as short as physically possible, matched in length, and routed as a pair with the ground plane beneath them unbroken.
No other signal should run beneath the crystal or between the crystal and the device. The load capacitors should sit on the far side of the crystal from the device, so that the current loop passes through the crystal and returns by the shortest route. A ground ring or a local flood around the oscillator, tied to the plane with several vias, reduces the coupling between the oscillator and the rest of the board, and the technique is described with its thermal implications in this discussion of copper flooding strategies.
Where the design uses an external clock instead of a crystal, the same rules apply with the addition that the clock trace should be kept away from the board edge and from any connector pin, since it is the fastest periodic signal on the board.
Boot, Reset and Configuration Circuits
The boot circuit is easy to place badly because it seems static. In reality the boot pins are sampled at reset, and the traces carrying them run close to the power pins and to the oscillator. Boot resistors should sit near the pins they configure, with short connections and a clean reference, so that the sampled level is unambiguous.
The reset network needs the same care. The reset line is slow, but a long trace with a capacitor at the far end forms a loop that can pick up noise from the surrounding circuitry. Keeping the reset capacitor and any pull-up close to the device pin, and keeping the trace away from the switching supplies, is usually enough.
Interfaces and Signal Quality
USB, Ethernet and any external memory interface bring their own requirements. Differential pairs must be routed with consistent spacing and consistent reference, and their length matching is a delay requirement rather than a cosmetic one. The routing rules that control which angles and which spacings are appropriate are described in this article on high frequency traces and data buses.
Where the core board exposes the microcontroller pins on headers, the escapes from the connector should leave the pad from its centre and continue in the direction the pad faces, so that repeated insertion and removal does not tear the trace. Series resistors on high-speed outputs, placed close to the driver, are a cheap way to control edge rate and reduce both ringing and radiated emissions.
A Practical Review List
Before releasing a core board layout, confirm that every power pin has a local decoupling capacitor with a short ground return, that the crystal loop is minimal and free of other signals, that the analog supply is filtered and its ground referenced at one point, that the boot and reset networks are close to the device, and that the ground plane under the high-speed interfaces is continuous. These five checks catch the majority of the problems that would otherwise appear during bring-up.
FAQ
How many layers does an STM32 core board need? Four layers is the practical minimum, arranged with a ground plane beneath the component side and a power plane below it. Six layers is preferable when the board includes external memory, USB or Ethernet, because the extra layers allow separate analog and digital references.
How close should the crystal be to the microcontroller? As close as the placement allows, with the traces matched in length and the load capacitors on the far side of the crystal. The parasitic capacitance of those traces adds to the load capacitance, so a long or asymmetric route changes the oscillator frequency and can prevent it from starting reliably.
Why does the analog supply need separate filtering? Because the digital switching activity on the main rail produces noise that appears directly on the analog reference and therefore in every measurement the analog circuitry makes. A ferrite or resistor with its own decoupling isolates the analog rail and keeps the reference quiet.
