Component Selection for PCB Prototypes: ESD and Latch-Up

A prototype board is only as robust as its most fragile component. Electrostatic discharge sensitivity, latch-up susceptibility and the behaviour of floating inputs are properties of the device selection and the surrounding network, not of the layout alone, and they mostly appear after the board is in the hands of a user rather than on the bench. Thinking about them during component selection costs almost nothing; fixing them afterwards usually means a respin or a hand-modified board that no longer matches the schematic.

ESD sensitivity is set by the weakest part

The static and discharge sensitivity of a whole assembly is determined by the component with the lowest threshold voltage, not by the average. Choosing devices with a high threshold where the function allows is therefore the first and cheapest protection step, because it raises the floor for the entire board and reduces the burden placed on external protection. Build the sensitive-part list during selection and review it before the bill of materials is frozen. Once the list exists, every interface that leaves the board, such as a connector, a long cable or a probe point, can be reviewed against the parts it touches. Protection works best when it is layered rather than concentrated. A series resistor at the connector, a clamp diode at the device pin and a short, low-inductance return path each remove part of the transient, and no single element has to absorb the whole event. That division of labour also makes the protection easier to tune, because the component closest to the connector can be changed without disturbing the device pin. Review the network as a chain from the connector inward, and confirm that each stage has a defined job rather than assuming the first component will handle everything. The layout side of the same problem is covered under ESD protection on PCB edge traces, since a discharge that reaches a trace will find the same device regardless of how carefully the network was chosen.

Understanding CMOS latch-up

Latch-up is a specific failure mode of complementary metal-oxide-semiconductor logic. The internal structure of these devices contains parasitic bipolar transistors, and the arrangement of a p-type and an n-type device next to each other forms a parasitic four-layer thyristor structure. That structure is a positive-feedback loop. An external event, such as a discharge or an over-voltage on an input, can inject enough current to start the loop, and the current then amplifies itself through the two parasitic transistors until the device is destroyed. The defence is to prevent the current from ever reaching the level that sustains the latched state, because once the loop closes the device will not release on its own.

Limiting output current

The standard remedy is to isolate each output from the outside world with a series resistor and to clamp the cable side to the supply rails with two fast switching diodes. The resistor limits the current that can be driven into the parasitic structure, and the diodes divert a transient to the rails before it reaches the device. The value has to be chosen against the output drive requirement and the capacitance of the cable; a resistor large enough to protect the device may also slow the edge enough to matter in a fast interface. That trade-off is a design decision, not a default, and it should be recorded with the schematic. The low-cost signal quality improvements that help here, such as controlled edge rates and short return paths, work in the same direction.

Filter networks for long cables

Long input cables between a circuit and a mechanical contact or an external system raise the probability of picking up electromagnetic interference, and they add distributed capacitance and inductance at the same time. That combination forms an LC network that can self-oscillate, and the oscillation can damage the protection diodes that are supposed to be protecting the device. A series resistor at the input, sized so that the current is limited to roughly 1 mA at the supply voltage, breaks the resonance and protects the clamp. The value follows directly from the supply rail divided by the target current, which makes it one of the few component choices that can be calculated rather than estimated.

RC networks on sensitive inputs

Where the input of a bipolar device is exposed to the outside world, an RC network is the standard mitigation. A relatively large series resistor combined with a capacitor of at least 100 pF slows the transient that reaches the device and absorbs part of its energy. The capacitor value is a compromise: a larger capacitor gives more protection but loads the input and limits bandwidth. For a slow control input the compromise is easy, and for a signal input the network has to be checked against the required response time. Place the capacitor close to the device pin and return it to the same reference the device uses, so the transient current does not have to travel across the board.

Never leave CMOS inputs floating

An unconnected CMOS input is not in a defined state. The input sits at an indeterminate potential, which breaks the logic relationship the circuit depends on and makes the device sensitive to noise pickup and to electrostatic damage. Every input pin must be driven or tied off, including the inputs of gates that are not used at all. Sweep the input pins of every device on the board as a checklist item before release, because a single overlooked one defeats the rest of the protection network. This is one of the most common review findings on a prototype, because an unused gate is easy to leave unconnected on the schematic and even easier to overlook on the board.

Handling unused inputs

Unused inputs should be tied to a defined level according to the function of the part. An unused gate input is normally tied to the rail that holds the output in the inactive state, either directly or through a resistor if the schematic needs the flexibility. A spare buffer can have its input tied to the appropriate rail and its output left open. Do not rely on an internal pull-up or pull-down unless the data sheet guarantees one across the full temperature range. Document the decision next to each unused pin on the schematic, so the review does not have to be repeated on the next revision. The mixed-signal design guidelines cover the related case of inputs shared between analog and digital domains.

Documenting the protection plan

Record the sensitive-part list, the series resistors, the clamp diodes and the RC networks in one place, and reference them from the assembly and test documents. That file is what allows a later board-level ESD test, against a standard such as IEC 61000-4-2, to be interpreted: a failure can be traced to a specific interface rather than to the board as a whole. Applying the manufacturable design guidelines at the same stage keeps the protection components in locations that can actually be assembled and reworked. gopcb reviews the protection network together with the placement, because a clamp diode placed far from the connector protects nothing.

FAQ

Why does one sensitive component decide the whole board rating? A discharge finds the easiest path, so the device with the lowest threshold will fail first regardless of how robust the rest of the board is. Selecting parts with a higher threshold raises the floor for the entire assembly.

Can latch-up be cleared by removing power? Sometimes, if the current is interrupted quickly enough. In many cases the device is damaged before power can be cycled, which is why the design aims to stop the current reaching the sustaining level rather than relying on recovery.

What resistor value should go in series with a long input? Size it so the current is limited to about 1 mA at the supply voltage, then check that the resulting RC time constant does not slow the signal beyond what the interface requires. The two limits usually leave a workable window.