High Speed Routing Requirements for PCB Layout

High speed routing is not a separate technique from ordinary routing. It is the same activity with additional constraints that become significant once the rise time of the signal is short enough that the trace behaves as a transmission line rather than as a wire. The constraints are few, and they are mostly about continuity.

When a Trace Becomes a Transmission Line

The relevant comparison is not the clock frequency but the rise time. A signal with a fast edge contains high frequency content regardless of how often it switches, and if the trace is long compared with the distance the edge travels during that rise time, reflections appear.

The practical guide is to treat a trace as a transmission line once its length exceeds roughly a quarter of the wavelength of the highest significant frequency in the signal. Below that, ordinary routing rules apply; above it, the constraints in this article take over.

Controlled Impedance

A trace has a characteristic impedance determined by its width, its distance to the reference plane and the dielectric constant of the material. When the source, the trace and the load are not matched, part of the signal reflects, and the reflection appears as ringing or as a false edge.

Impedance control therefore means choosing a stackup whose dielectric thicknesses produce the target impedance for the widths the layout needs. It is a stackup decision as much as a routing one, and it must be made before the layout starts. The structural implications are covered in our layer assignment notes.

Reference Plane Continuity

Every high speed trace needs a reference plane directly beneath it, and that plane must be continuous along the whole length of the trace. A trace that crosses a plane split has no defined impedance over the crossing, and the return current has to find another way.

The common failure is a signal that changes reference planes through a via without a stitching capacitor nearby. The return current then has to travel across the board to find a path, which turns a short trace into an unintended antenna. Providing a nearby stitching via or capacitor at each transition restores the path.

Matched Length and Skew

Where several traces carry a signal that must arrive together, their lengths must match within a tolerance derived from the timing budget. The allowance is not arbitrary: it depends on how much skew the receiving device can tolerate and how much of the budget the other contributors have already consumed.

Differential pairs add a second condition. The two traces must be matched to each other as well as to the other pairs, because an imbalance converts part of the differential signal into a common mode signal, which radiates and which the receiver rejects poorly. Length matching within a pair should be done where the skew occurs, not accumulated at one end.

Crosstalk and Spacing

Crosstalk couples energy from one trace into another, and it grows as the traces get closer and as the parallel run gets longer. The three available controls are spacing, the length of the parallel run and the height above the reference plane.

Routing adjacent traces closer to the plane reduces coupling significantly, because the fields are confined to a smaller volume. That is why thin dielectrics help high speed designs more than wide spacing does, and why the stackup decision affects crosstalk as much as the routing does. The impedance consequences of the same choice are described in our transmission line article.

Vias and Their Effects

A via is a discontinuity. It adds capacitance where it passes through the planes and inductance along its barrel, and in a thick board the unused portion of the barrel becomes a stub that resonates at a frequency the signal may contain.

Back drilling removes the unused stub, and blind or buried vias avoid creating it in the first place. Both cost money, and the decision should follow from the highest significant frequency in the design rather than from a general preference for better vias.

Termination and Topology

Where a trace is long enough to reflect, termination at the source or at the load absorbs the reflection. Series termination at the driver is cheap and effective for a single load, while parallel termination at the receiver works for a bus with several loads.

The topology of the bus follows from the same reasoning. A daisy chain with short stubs behaves differently from a star, and the choice depends on where the loads are and how fast the signal is. Deciding the topology before routing the bus is what prevents the stubs from being discovered after the layout is finished.

Trace Length and the Timing Budget

Trace length matching is not an end in itself. It exists to keep the skew between signals within the timing budget of the interface, and the budget is shared among several contributors.

The receiver setup and hold window, the output skew of the driver, the package delays and the board skew all consume the same allowance. Working out how much is left for the board is what turns a length matching rule into a number, and a number can be met with confidence. Our design tolerances article describes how such a figure is recorded.

Layer Transitions

Every transition between layers is an opportunity to lose the reference. Where a trace moves to a layer whose reference plane is a different net, the return current has to find a path between those two planes.

A stitching via or a capacitor placed beside the signal via provides that path. The distance matters: a stitching point several millimetres away is no longer adjacent, and the loop it creates is large enough to radiate. Our notes on blind and buried vias describe the structural options for reducing transitions in the first place.

Materials at High Frequency

Above a certain frequency, the dielectric loss of the laminate becomes a significant part of the total loss along a trace. Standard FR-4 is adequate for many interfaces and inadequate for the fastest ones.

Low loss laminates reduce that loss and also provide a more consistent dielectric constant, which makes impedance control easier to hold. The decision follows from the interface specification and from the trace lengths involved, and it should be made together with the stackup rather than afterwards. Our high Tg material notes cover the related thermal consideration.

Where the board must carry several interfaces with different requirements, the strictest one does not have to govern the whole layout. Applying the matching rule only to the buses that need it, and leaving the rest at ordinary spacing, keeps the board routable.

FAQ

Does a slow clock need high speed routing rules? If its edges are fast, yes. The rise time sets the frequency content, and the clock frequency does not.

How long can a stub be before it matters? It depends on the highest significant frequency. As a rule of thumb, a stub shorter than about one tenth of the wavelength of that frequency is usually tolerable.

Is differential routing always required for high speed? It is required where the interface specifies it or where common mode noise must be rejected. Many single ended high speed signals are routed with impedance control only.