Active Crystal Oscillator Selection for Industrial Boards

An oscillator is one of the few components whose error budget cannot be corrected elsewhere in the system. A voltage reference can be calibrated, a sensor can be linearised, but the clock that drives a converter, a radio or a serial link defines the time base that everything else is measured against. Choosing one is therefore a specification exercise: the frequency is the least interesting number on the datasheet, and the tolerance, jitter and supply behaviour are the ones that decide whether the design works.

Small active oscillators have changed this calculation. A four-pin package measuring 2.5 mm by 2.0 mm can now cover an industrial temperature range from a supply that spans 1.62 V to 3.63 V, which means the same part can serve a 1.8 V and a 3.3 V platform. That flexibility removes a second part number from the inventory, but it also removes the excuse for not reading the specification carefully.

What an Active Oscillator Datasheet Tells You

An active oscillator contains the resonator, the oscillator circuit and an output driver in one package, so it delivers a logic-level square wave rather than a small sine wave that the processor must amplify. The specification therefore describes a complete clock source: output levels, load capability, duty cycle, rise and fall times, supply current, startup time and the accuracy of the frequency itself.

A representative industrial part might specify a CMOS output driving a 15 pF load, a duty cycle between 45 and 55 percent, rise and fall times of no more than 5 ns, an output high level above 90 percent of the supply and a low level below 10 percent. Those numbers mean the output can drive a controller or PHY clock input directly, without an external matching network or level shifter, which is why the surrounding circuit in a modern design is little more than a decoupling capacitor.

Supply and Enable Behaviour

Wide supply range is the feature that reduces part count. A device specified from 1.62 V to 3.63 V can be used on a 1.8 V rail and on a 3.3 V rail without a design change, and the specification applies across the whole range rather than to a nominal voltage. Maximum supply current in the region of 10 mA is typical for a small oscillator, which is low enough for most battery-powered gateways but still worth including in the power budget of a design that sleeps for long periods.

An enable pin is more useful than it appears. Where the output is enabled above 0.7 of the supply and disabled below 0.3 of the supply, a GPIO can gate the clock, which removes the need for a separate clock switch and its added skew. Enable delay is typically a small fraction of a millisecond, so the clock returns quickly after wake-up. The behaviour with the pin floating must be checked, because an oscillator that defaults to off will not start on a board where the pin is left unconnected.

Frequency Tolerance Over the Full Range

A tolerance quoted at 25 degrees Celsius describes almost nothing about field behaviour. What matters is the frequency tolerance over the entire operating temperature range, because a timing budget that is met in the laboratory can fail in an outdoor cabinet. An industrial crystal oscillator is typically specified within about plus or minus 20 ppm at room temperature and within about plus or minus 30 ppm from minus 40 to plus 85 degrees Celsius, with an aging figure in the region of plus or minus 3 ppm per year.

Those three numbers should be added, not chosen individually. The total error at end of life is the initial tolerance plus the temperature excursion plus the accumulated aging, and for a serial link the resulting ppm budget must fit inside the allowance of the protocol. A part that looks comfortable at 25 degrees can be marginal after five years in a hot enclosure, and the calculation is trivial compared with the cost of a field failure.

Layout for Low Jitter

An oscillator’s phase jitter is quoted on the datasheet, but the value measured on a board is usually higher, because supply noise and coupling add to it. The two layout measures that protect the figure are decoupling and separation. Place the decoupling capacitor immediately adjacent to the supply pin with the shortest possible return path, and route the oscillator supply from a quieter rail rather than sharing a branch with switching regulators or motor drivers.

Keep the output trace short and treat it as a controlled transmission line when the frequency warrants it, following the practice for high frequency trace routing. Avoid layer transitions on the clock net, since each one introduces an impedance discontinuity that distorts the edge. Do not route the clock under the oscillator body or close to a crystal load capacitor, and keep the ground plane solid beneath the package. Thermal separation also matters: an oscillator placed next to a power device drifts with it, so the placement discipline of thermal management PCB design applies to the clock source as well.

Where Oscillator Error Shows Up

The consequences of clock error depend on the function. In an analogue-to-digital converter, jitter in the sampling clock appears as a rise in the noise floor that grows with input frequency, reducing the effective resolution even when the converter itself is adequate. In a serial link, the same jitter consumes eye margin. In a radio, frequency error shifts the carrier and degrades the constellation, while phase noise broadens the carrier and increases adjacent channel interference.

A clock source should therefore be selected against the requirement of the most sensitive load, not against an average. Once chosen, the design should be verified with the clock measured at the load, as described in PCB design quality characteristics, and the measurement should be repeated over temperature if the product is specified for an industrial range.

Startup, Sleep and Gate Behaviour

Startup time is a specification that is easy to ignore until a design has to wake from a low power state. An oscillator that takes a few milliseconds to reach a stable output delays every wake-up, and a controller that begins to use the clock before that time has elapsed will run on an unstable frequency. Check the maximum startup time against the system requirement and, where the clock is gated by an enable pin, add the enable delay to the figure before deciding that the supply can be removed between transactions.

Gating the clock with a GPIO is a useful low power technique, but it changes the relationship between the clock and the rest of the system. Verify that the peripheral expecting the clock tolerates its absence, that the first edges after re-enable have the same quality as the steady state, and that the control signal itself is clean, since a slow or noisy enable transition can produce a runt clock pulse that some receivers will accept and act on.

FAQ

Should a design use an active oscillator or a crystal with an internal driver? Use an active oscillator when the accuracy and jitter requirement is specific, when board space is scarce, or when the processor clock circuit is not well characterised. A crystal with the internal driver costs less but depends on load capacitor selection and layout that are harder to control.

Does a wider supply range cost anything? It can slightly reduce the output edge rate at the low end of the range, because the drive current is fixed while the required swing scales with the supply. Verify the rise time at the minimum supply voltage, not at the nominal one.

How should the enable pin be treated if it is not used? Tie it to the state that enables the output, and check the datasheet for what a floating pin does. Leaving it unconnected on a part that defaults to disabled produces a board with no clock and no obvious fault.