Planning an HDI Microvia Stackup Before Layout

High density interconnect is often described as making the holes smaller, but that description misses the point. The real change is that the layer structure becomes a design variable rather than a fixed frame: the number of build-up layers, the thickness of each dielectric, and the type and depth of every via have to be chosen together with the routing plan. A microvia stackup decided after the layout is drawn is a stackup that will either cost more than necessary or fail to route.

The starting point is the device that has to be escaped. Fine pitch ball grid arrays determine how many connections must leave a small area, which determines how many routing channels are needed per layer, which in turn determines how many build-up layers are required. Working backwards from that requirement is far more reliable than choosing a stackup from a catalogue and hoping the routing fits.

Choosing the Build-Up Structure

The common notations describe how many sequential build-up layers sit on each side of the core. A single build-up layer per side is the simplest and least expensive structure and is adequate for moderate density. Two layers per side provide more routing channels and suit complex escape patterns and high speed interfaces. Three or more layers are used for the densest products, with a corresponding increase in lamination cycles, registration difficulty and cost.

The structure should be the simplest one that routes. Adding a build-up layer to gain routing freedom increases the number of press and plating cycles, worsens the accumulated registration error, and raises the cost per board. Where a design appears to need a third build-up layer, the first question should be whether the routing requirement itself can be reduced by moving a device, changing a package pitch, or reallocating the layer assignment.

Blind and Buried Vias Need Planning Early

A blind via connects an outer layer to an inner layer without passing through the board, and a buried via connects inner layers only. Both free routing space that a through via would consume, and both impose constraints that must be respected during layout. The laser drilled microvia in particular has a limited depth for a given diameter, expressed as an aspect ratio, and staying inside that limit keeps the plating process reliable.

Dielectric thickness is the other constraint. A build-up layer that is too thick makes the via deeper than the laser can reliably process, while a layer that is too thin reduces the impedance control range available for the traces on it. Stacked vias, where one microvia sits directly on another, require the lower via to be filled and planarised, and staggered arrangements relax that requirement at the cost of routing space. Deciding which approach is used, and where, belongs in the stackup plan rather than in a late layout decision.

Signal Integrity Consequences of the Stackup

Thin build-up dielectrics change the impedance calculation. A trace on a build-up layer sits closer to its reference plane than a trace on a conventional layer, so for the same characteristic impedance it must be narrower, which reduces the copper cross section and raises the conductor loss. This is one reason a stackup cannot be copied from a previous project without recalculating the geometries, even when the layer count is the same.

Via structures also affect the channel. A microvia that reaches only the first few layers has no stub below its exit point, which is an advantage over a through via at high frequency, but a stacked arrangement introduces an additional transition and its own small discontinuity. Where the design carries high speed interfaces, the stackup plan and the impedance plan should be produced together, and the transitions that matter are those described in impedance discontinuity analysis.

<img src="https://www.gopcba.com/wp-content/uploads/2026/06/DWDM波分复用设备-PCBA.jpg" alt="BGA escape routing planned against the microvia stackup” />

Coordinating With the Fabricator

Microvia capability is not standardised across suppliers. The achievable aspect ratio, the minimum laser drilled diameter, the maximum number of sequential laminations and the fill quality all vary, and a structure that one supplier builds routinely may be outside the process window of another. The stackup should therefore be confirmed against a specific supplier’s capability before the layout is committed, not after the file has been released for quotation.

The options available for high density construction are described in any layer HDI and in the general treatment of high density interconnect design, and the filling process that makes stacked vias possible is covered in PCB via plugging. Documenting the stackup, the via types and the fill requirement in those terms turns a design intent into a manufacturable instruction.

Escaping a Fine Pitch Device

The escape pattern is where the stackup requirement originates. A ball grid array with a pitch small enough that only one trace can pass between adjacent balls forces the inner rows to be reached through vias, and the number of layers needed to route those vias out determines the build-up structure. Planning the escape before the stackup avoids the situation where the stackup is adequate for the general routing but not for the area around the device.

A larger package pitch can reduce the requirement substantially, at the cost of board area, and the trade should be evaluated with the stackup cost in view rather than in isolation. Where the device cannot be changed, the escape plan and the via types have to be designed together, and the sequencing described for escape routing and fanout is the appropriate starting point.

Documenting the Stackup for Handoff

The stackup plan should leave the design as a document rather than as a set of intentions. A drawing that states the build-up order, the dielectric material and thickness of each layer, the copper weight, the via types with their diameters and depths, the fill and planarisation requirement and the impedance targets gives the fabricator everything needed to quote and build the board without asking a question. It also gives the next engineer a starting point for a revision.

Two details are frequently omitted and frequently costly. The first is the reference plane assignment for each signal layer, which determines the impedance calculation and must be stated so that it is not changed by the fabricator when the construction is optimised. The second is the requirement for test coupons, since impedance, plating thickness and microvia structure can only be measured on a coupon that the fabricator knows to include.

Keeping that document current is part of the same discipline. When the stackup changes during a revision, the via types and the impedance targets usually change with it, and a drawing that is updated only in part produces a board that matches neither the previous design nor the new one.

FAQ

How many build-up layers does a design need? As many as the escape pattern and the routing density require, and no more. Each additional build-up layer adds lamination cycles, registration difficulty and cost, so the simplest structure that routes is the correct answer.

Can a microvia be stacked directly on another? Yes, provided the lower via is filled and planarised so that the upper via has a flat, sound base. A void or a deep dimple in the first via becomes a defect in the second.

Why does dielectric thickness matter for the laser? Because the laser has to reach the target pad without damaging it. A thicker dielectric requires more energy, which narrows the process window and increases the risk of punch-through.