Level Shifter Interface Circuit Design
Modern boards mix logic families, and a 3.3 volt processor often has to talk to a 5 volt peripheral or a 1.8 volt radio. Connecting them directly risks both damage and unreliable operation, so a level shifter is inserted between the two domains. The circuit is small, but the choice of topology decides whether the interface works over temperature and at the required speed.
Why Level Translation Is Needed
A logic input has a threshold that lies somewhere between its supply rails, and an input driven above its own supply can forward bias a protection diode inside the device. That condition allows current to flow from the higher domain into the lower one, which can power the lower rail through the signal pin and leave the device in an undefined state.
Even where the absolute maximum ratings are respected, the thresholds may not be. A 3.3 volt output driving a 5 volt input may not reach the input high threshold, while a 5 volt output driving a 3.3 volt input may exceed the maximum input voltage. Both problems appear as intermittent failures that depend on temperature and on the tolerance of the parts.
voltage translation also has to preserve the timing of the signal. A shifter that adds different delays to the rising and falling edges changes the duty cycle of a clock or a pulse width modulated signal, which can matter more than the absolute delay in some applications.
Common Level Shifter Topologies
A dedicated level shifter integrated circuit contains the translation circuit and, usually, the direction control. It is the simplest solution when the direction is fixed and the supply rails are known, and the propagation delay is specified, which makes timing analysis straightforward.
A discrete translator built around a single transistor is used for open drain buses such as I2C, where the same line is driven from both sides. The transistor is arranged so that the line is pulled low by either side and the pull up resistors restore the high level in each domain, which makes the circuit inherently bidirectional without any direction control.
A series resistor with a clamp diode is sometimes seen in low cost designs as a way of translating a 5 volt signal down to 3.3 volts. It works only at low speed, because the resistor and the input capacitance form a delay, and it relies on the clamp diode to absorb the excess current, which is a state the part is not designed to remain in. It is acceptable as a temporary measure during development and a poor choice for production.
Open Drain and Bidirectional Buses
An open drain bus has no active pull up, so the rise time is set by the pull up resistor and the capacitance of the line. That makes the topology inherently slow at the high level, and the value of the pull up resistor becomes the main design decision. A small resistor gives a fast rise but draws more current when the line is low, while a large resistor saves current and produces slow edges that may violate the timing of the bus.
Where two domains share an open drain bus, the pull ups for each domain are separate, and the translator provides the connection between them. The two pull ups are effectively in parallel when the bus is high, so the combined value has to be calculated rather than the individual values being used independently.
push pull outputs are used where the direction is fixed and the speed requirement is high. A push pull translator can drive the line in both directions actively, which gives fast edges and defined levels, at the cost of requiring a direction signal or of being unidirectional. On a bus that can be driven from either side, a push pull translator without direction control will produce contention.
Propagation Delay and Skew
propagation delay is the time between a change at the input and the corresponding change at the output, and it is usually specified with a maximum value over the temperature range. Where the shifter sits in a timing critical path, that delay has to be included in the budget for the interface along with the delays of the driver and the receiver.
Skew between channels matters more than the absolute delay in parallel buses. If a shifter introduces different delays on different bits of a byte, the data arrives with different amounts of skew, which reduces the setup and hold margin at the receiver. A device with a specified channel to channel skew makes that analysis possible.
For clock signals the duty cycle distortion is the more important parameter. A shifter that delays the rising edge more than the falling edge changes the duty cycle, and a clock that must stay within a narrow tolerance may be pushed outside it. Checking the device specification for output duty cycle, and measuring it where the signal is critical, is worth the time.
Supply Sequencing and Partial Power Down
A level shifter sits between two supplies, and it is affected by how they come up. If one side is powered and the other is not, current can flow through the device unless it is designed to tolerate that condition. Many shifters specify a partial power down condition in which one side is at zero volts and the other is normal, and the current drawn has to stay within a limit.
Choosing a device with that capability removes the need to sequence the two supplies for the interface, which simplifies the power design. Where the device does not support it, the two rails have to come up together or the interface has to be disabled until both are present. A series resistor in the signal path limits the current but also slows the edge.
The enable pin, where one is provided, should be driven from a signal that is valid in both domains, which usually means from the lower voltage side. Driving the enable from a rail that is not yet present leaves the device in an undefined state, and the resulting behaviour is difficult to reproduce because it depends on the exact ramp rate of that rail.
Layout and Signal Integrity
Keep the shifter close to the receiver that needs the translated level, and keep the two domains separate on the board so that the reference for each signal is clear. A trace that runs from a 1.8 volt area into a 3.3 volt area crosses a boundary, and that boundary should be crossed once rather than the signal wandering between the two regions.
Decouple both supply pins with a ceramic capacitor placed within a few millimetres, and avoid sharing a decoupling capacitor between a shifter and a switching regulator. The currents drawn by a fast level translator are small but fast, and a shared capacitor with a long connection does not supply them effectively.
Where the signal leaves the board, treat the translated output as a normal interface signal and apply the usual protection and filtering. The general approach to keeping a signal clean as it crosses between domains and out of the enclosure is described in EMI suppression design, and the partition between analogue and digital areas in mixed signal board design applies to the two logic domains as well.
Verification and Common Faults
Measure the levels at the input of the receiving device rather than at the output of the driver. The question is whether the receiver sees a valid high and a valid low, and the trace and the connector between the two points are part of the answer. A signal that looks healthy at the driver can be marginal at the receiver.
Check the current drawn by the interface with one supply removed, if the design claims partial power down support. A few microamperes are acceptable, while a milliampere indicates that current is flowing through the signal pins and that the device is being powered through its inputs.
A shifter that works at room temperature and fails when the equipment warms up is usually operating close to a threshold. The output levels of a translator move with temperature and with load, so a design that relies on the typical specification will fail at the extremes. Comparing the measured levels with the receiver thresholds at both temperature extremes settles the question, and the manufacturing notes in manufacturable PCB design cover the test access that makes those measurements practical on a production board.
FAQ
Can I connect a 5 volt output to a 3.3 volt input through a series resistor alone? It works only where the 3.3 volt device has a clamp diode and the current is limited to a safe value. It is slow, and it is not a production solution.
Do I need a level shifter for a 3.3 volt output driving a 5 volt input? Often yes, because the 5 volt input threshold may be above 3.3 volts. Check the input high threshold of the receiving device against the output high level with the worst case load.
How do I choose the pull up value on a translated open drain bus? Start from the required rise time and the total line capacitance, then confirm that the resulting current when the line is low is within the driver rating.
