PCB Design Around a High-End Applications Processor

A high-end applications processor is no longer a single chip surrounded by a few peripherals. It is a small system: several high-speed serial links, a display pipe, a memory controller that wants its own stack-up, and a power architecture with a dozen rails that must come up in a defined order.

This article works through the board-level consequences of that integration. It covers the interfaces that need controlled impedance, the memory escape that dominates routing area, the storage attachment, and the thermal design that decides whether the part can run at its rated speed at all.

What a Modern Applications Processor Demands From the Board

The interfaces on a current-generation part fall into three groups. The first is differential serial: USB, PCI Express and display links, all of which live or die by impedance control and by the quality of the return path under them. The second is parallel memory, which needs matched lengths, a clean reference plane and a great deal of routing area. The third is low-speed control and power, which is easy to route but just as easy to route badly.

What makes the layout difficult is that the groups compete for the same real estate and the same ground. The memory bus wants a solid plane under it and a quiet return. The serial links want to keep their reference continuous from driver to receiver. The power delivery network wants copper. On a board that is also thin, all of these demands are met in a stack-up of eight to twelve layers, which is why an FPGA board designed for high-speed interfaces ends up looking structurally similar to an applications processor board.

USB Type-C and the Power Side of the Connector

The USB Type-C connector carries two jobs that have to be designed separately. The first is the high-speed pair, which is a standard differential channel and wants the usual treatment: a defined impedance, a ground reference that does not switch planes, and length matching between the two conductors of the pair. The connector pinout is compact enough that escape routing is the hard part rather than the impedance itself.

The second job is power and configuration. USB Type-C can negotiate a much higher current than the older connectors, which turns the connector area into a thermal and copper problem as well as a signal problem. The VBUS path needs enough copper to keep the temperature rise within the connector rating, and it needs the negotiation and protection circuitry close to the pins. A narrow VBUS trace that looked adequate on paper is one of the more common reasons a prototype runs warm at the connector.

MIPI Display and Camera Interfaces

The MIPI interface used for displays and cameras is a set of narrow differential lanes running at high speed over a short distance. Individually the lanes are undemanding compared with a long PCI Express channel, but there are many of them, they are routed close together, and they share a package ballout with everything else, so crosstalk and escape routing dominate the design rather than attenuation.

Two rules cover most of the risk. Keep each lane pair tightly coupled and matched within a few mils, and keep the spacing to the neighbouring pair at least three times the trace width on the same layer. Where a display connector sits on a flex tail, the transition between rigid and flexible sections must maintain the reference plane, which is where most of the real-world failures come from.

LPDDR4 Memory and Escape Routing

LPDDR4 memory trades the wide parallel bus of a desktop design for a narrower one running at a higher rate, but it still needs matched routing and a continuous reference. The usual approach is to route the memory on the layers immediately adjacent to a solid ground plane, with the data byte groups matched within each group and the clock and strobe treated as the reference for their group.

Escape routing under the package is where the layer budget is spent. A fanout that spreads the balls out layer by layer, rather than trying to escape everything on the first inner layer, keeps the channel lengths short and the via count low. Where a via has to be placed inside a pad, an in-pad via against the plated-through alternative is worth a deliberate decision, because the two have very different effects on assembly yield.

PCIe and Storage Attachment

PCI Express is the interface most likely to be the limiting factor on a thin board edge. Its loss budget is defined with a specific channel in mind, and an escape route that adds two vias and a long connector stub can consume most of it. The practical response is to keep the transmit and receive pairs on the same layers from start to finish, and to place any coupling capacitors close to the driver so the discontinuity sits where there is still margin.

When several lanes are bundled, they are usually routed in a group with the pairs length-matched to each other. The matching rules used for serpentine routing apply directly here, including the requirement that the serpentine sits on a solid reference plane, because a zigzag routed over a plane split turns a harmless length adjustment into a crosstalk source.

Thermal Design in a Thin Enclosure

A handset-class applications processor dissipates enough heat that the enclosure, not the chip, becomes the limiting factor. The thermal design therefore starts with the mechanics: how much copper can be placed under and around the package, how much of it connects thermally to the frame, and whether the board can act as a spreader rather than an insulator.

The most effective moves are usually thermal vias under the exposed paddle and a copper area large enough to spread the heat before it reaches a temperature-sensitive neighbour. Removing copper from an inner layer to make room for a signal often seems free and is not, because the inner planes are also the heat path. A quick thermal estimate during layout is far cheaper than discovering the limit during the first full-load test.

Power Sequencing, Decoupling and Bring-Up

An applications processor has a defined power-up order, and the rails must arrive within the sequence and the timing window the datasheet specifies. Violating the order may not damage the part, but it will leave it in an undefined state, producing a board that appears not to boot and sends the bring-up effort in the wrong direction entirely.

Decoupling is the other half of a stable bring-up. The small-value capacitors belong as close to the package as the layout allows, on the same side where possible, with the larger bulk capacitance placed where it can serve several rails. Keeping the loop area small matters more than the total capacitance value, so the return path from each capacitor to the package ground should be short and uninterrupted on the reference plane beneath it.

FAQ

How many layers does an applications processor board need? Most designs converge on eight to twelve layers once the memory bus, several differential channels and a solid reference plane have been accounted for. The count is driven by how many signals must be referenced to an uninterrupted plane, not by the ball count of the package alone.

Can the MIPI lanes share a ground plane with the DC-DC converter? They should not share the same local ground area. The converter switches large currents and creates a voltage gradient across the plane, so route the display and camera lanes over a plane that is continuous and return them to a quiet ground reference.

What is the first thing to check if the board does not boot? The power-up order and the reset timing, before changing any layout. A sequence fault produces the same symptom as a signal-integrity problem, and it is far quicker to rule out with a scope on the rails than to chase a routing issue that does not exist.