FPGA Board Design for High Speed Interfaces
An FPGA is not simply a large component. It is a system on a package, with dozens of high-speed serial channels, several parallel memory interfaces and a power demand that changes faster than any regulator can respond to. The board that carries it has to deliver power across a wide frequency range, maintain impedance on channels running at tens of gigabits per second, and remove heat from a device that may dissipate more than the rest of the board combined.
Start With the Data Sheet Limits
Three numbers from the device data sheet drive the whole design. The maximum transceiver rate per channel determines the required material, the loss budget and the number of layers. The maximum transient current, expressed as the rate of change of current, determines the decoupling strategy and the geometry of the power distribution network. The maximum junction temperature determines the thermal solution and therefore the mechanical arrangement of the board.
None of those limits can be discovered late. A design that assumes a standard laminate and then finds that the channel loss at the target rate is too high must change the material, which changes the stackup, which changes every impedance calculation and every trace width. The material decision is the first decision, and it follows from the transceiver rate.
SerDes Channels
High-speed serial channels are differential, impedance controlled and loss limited. The routing must maintain constant differential impedance, matched length within each pair and a controlled reference plane beneath the pair for the whole route. Where the channel passes through a connector, a via field or an AC coupling capacitor, the discontinuity at that point must be small relative to the loss budget and it must be characterised rather than assumed.
Via transitions deserve particular attention. A signal via that changes layers without a nearby ground via forces the return current to find another path, adding inductance exactly where the impedance is already disturbed. Placing ground vias adjacent to the signal via, and using a back-drilled or blind structure to remove the unused stub, are the standard treatments. The rules that govern the geometry around those vias are set out in this article on via to trace clearance.
Trace length also matters for loss, not only for timing. At the frequencies involved, the dielectric loss per unit length is significant, and a route that is longer than necessary consumes part of the loss budget that might be needed later for a connector or a cable. Keeping the channels short is a design objective in its own right.
Memory Interfaces
The DDR interface on an FPGA board is a different problem from a serial channel. A parallel memory interface is a group of single-ended nets routed with controlled impedance, matched in length within a byte lane and referenced to a plane that does not jump between the controller and the memory. The routing is wide, the nets are numerous, and the discipline required is the group discipline described in this discussion of high frequency traces and data buses. It is a group of single-ended nets that must be routed with controlled impedance, matched in length within a byte lane, and referenced to a plane that does not jump between the controller and the memory. The routing is wide, the nets are numerous, and the discipline required is the group discipline described in this discussion of high frequency traces and data buses.
Termination on a DDR interface is usually integrated into the device, but the reference voltage and the address and control nets still need care. The VREF plane or trace must be quiet, because any noise on it appears directly in the sampling threshold. Keeping VREF away from the switching supplies and decoupling it locally is a small effort with a large effect.
Power Integrity and Sequencing
The core supply of a large FPGA draws current in bursts that no regulator can follow in real time, which is why the decoupling network exists. The network has to present a low impedance across a band that extends from a few kilohertz to several hundred megahertz, and achieving that requires capacitors of several values placed close to the device rather than a single large capacitance somewhere on the board.
The plane pair beneath the device is part of that network. Its capacitance and its inductance set the impedance at the highest frequencies, and the vias that connect the device to the planes set the impedance at the transition. Reducing the loop area between a power pin and its ground pin is the single most effective layout action available, and it is a placement decision rather than a routing one.
Sequencing is the other power consideration. Most large devices require their rails to come up in a defined order and to reach their nominal values within a defined time, and the design must provide the circuitry that enforces this. Where the requirement is handled by an external sequencer, its outputs must reach the regulators without picking up noise, and the feedback paths of the regulators must return to a quiet reference.
Thermal Design
A large FPGA dissipates tens of watts, and almost all of it leaves through the package base into the board. The thermal design therefore starts with the copper beneath the device: a thermal pad region on the top layer, a dense array of thermal vias through the board, and a copper region on the bottom layer or an attached heatsink. The vias must be sized and spaced so that the paste is not starved during assembly, since a thermal pad with poor solder coverage has a thermal resistance far higher than its specification suggests.
Airflow and mechanical support complete the picture. A board carrying a large device with a heatsink attached will be loaded mechanically as well as thermally, and the mounting arrangement should avoid transmitting that load into the solder joints of the device itself.
Layout Review for an FPGA Board
Before release, confirm that every high-speed channel has a continuous reference, that ground vias accompany every layer transition, that the memory nets are matched within their groups, that decoupling capacitors sit at the pins they serve, and that the thermal path from the device has been verified on the artwork rather than assumed. Those five checks address the failure modes that dominate FPGA bring-up, and each of them is cheaper to correct at layout than after assembly. The stackup decisions they depend on are described in this article on layer stackup design.
FAQ
How do I know which laminate an FPGA board needs? It follows from the transceiver rate and the channel length. Higher rates and longer channels consume more of the loss budget, and the material loss tangent determines how much of that budget the dielectric uses. The data sheet gives the channel loss the device can tolerate, and the rest is calculation.
Why does an FPGA need so many decoupling capacitors? Because it draws current in bursts that extend over a very wide frequency range. Capacitors of different values cover different parts of that range, and each must be close to the pins it serves, since the inductance of the connection determines the frequency above which the capacitor stops being effective.
What is the largest layout risk on an FPGA board? The via transitions on high-speed channels. A transition without an adjacent ground via, or with an unremoved stub, introduces an impedance discontinuity and a resonance exactly where the signal is least able to tolerate either.
