COM Express Carrier Board Layout Guide
One way to shorten an embedded hardware programme is to stop designing the computer and start designing around it. A compute module packages the processor, its memory and the essential interfaces onto a small board with a standardised connector; the product-specific circuitry lives on a carrier board underneath. For a COM Express design, practically all of the layout risk moves to that carrier.
What the Module Contains, and What It Leaves Out
The module carries the processor, memory and necessary input and output interfaces in a compact footprint. What it deliberately omits is the bulk of the expansion and product-specific content: the connectors that face the outside world, the storage, the application circuitry and the power input stage all belong to the carrier.
The division matters because it defines the interface. Everything crossing between the two boards does so through a single high-density connector, which is simultaneously the design’s greatest convenience and its greatest layout challenge.
Why Teams Choose the Module Approach
Three advantages drive the decision.
Flexibility and scalability come first. Because the module carries processor, memory and storage options, a design can be configured for different performance points without redesigning the carrier, and upgraded later by changing the module rather than the whole system.
Second is standardisation. The interface is defined, so modules from more than one supplier can be compatible with a single carrier, and the development effort that would have gone into processor and memory design is spent elsewhere. Because the module can be reused across projects, the non-recurring engineering cost is shared rather than repeated.
Third is serviceability. A replaceable compute module makes maintenance and hardware upgrades quick, which reduces downtime and extends the working life of the equipment around it.
Layout Priorities for the Carrier
The carrier has a small number of decisions that dominate everything else.
Connector placement comes first, and it is mechanical before it is electrical. The mating connector fixes where the module sits relative to the board edge, which in turn fixes where the external connectors can be, which fixes the routing topology. Choose the connector location late and every other constraint is solved around a mistake.
The connector also brings keep-outs. There is usually limited clearance between the module and the carrier beneath it, so only low-profile components can be placed in that region, and a tall part in the wrong place makes the assembly impossible. Mounting and standoff positions, board thickness and stiffening requirements all belong to the same mechanical picture.
Thermal design is part of it too. Heat leaves the module through a defined path, and the carrier is normally expected to help conduct it away — through copper, through stiffeners, or into a housing. Treating the carrier as purely electrical tends to produce a design that works on the bench and throttles in the enclosure, which is the same trap described in this note on thermal management on dense boards.
Escaping the Connector
The module connector is dense and fine-pitch, and every signal on it has to leave the pin field. The escape pattern chosen directly beneath and around the connector sets the difficulty of everything that follows, and it is usually the point at which the layer count is decided.
The pinout is grouped by interface, and that grouping is a gift: high-speed pairs arrive on adjacent pins, power and ground arrive on blocks of pins, and low-speed signals are separated. Routing to take advantage of that grouping — fanning out whole interfaces together, keeping pair grouping intact through the escape, and distributing power pins through plane connections rather than long traces — keeps the board tractable.
If the escape requires more layers than the application circuitry does, the stackup should be chosen for the connector rather than for the rest of the board. The usual approach is to assign the signal layers around a continuous ground reference for the fastest interfaces and then place the remaining signals on what is left, as described in this discussion of multilayer layer assignment.
High-Speed Interfaces Across the Connector
Serial interfaces such as PCI Express, USB, SATA, DisplayPort and Ethernet all cross the module connector as differential pairs, and each brings its own constraint set.
Impedance and reference. Each pair requires a controlled differential impedance and a continuous ground reference from the connector pin through to its destination. The reference is the part that is most often broken: a pair that begins over a ground plane, crosses a power region, and continues over a different plane has been through two reference changes and two discontinuities, and the resulting common-mode conversion will show up in compliance testing rather than on the bench.
Length matching. Intra-pair matching is mandatory, and inter-pair matching is required wherever the interface defines a timing relationship between lanes. The tolerance comes from the interface specification, not from convenience, and the matching is normally done in the region between the connector and the device rather than along the whole path.
Layer transitions. Every via is a discontinuity, and on these interfaces the transition should be minimised, and where it is unavoidable, the via should match its neighbours in size, antipad and distance to the reference plane. Where the transition passes through unused layers, the resulting stub can resonate within the signal bandwidth unless it is designed out or terminated.
Crosstalk. Many pairs leave the connector in parallel. Maintaining pair-to-pair separation, avoiding long parallel runs on a single layer, and inserting ground between adjacent pairs keeps coupling inside the budget.
Power Delivery
A module draws several rails through the same connector, and the low-voltage rails carry high current. Three consequences follow.
The first is copper. Current-carrying capacity has to be sized for the rail’s continuous current at the permitted temperature rise, which means planes or thick traces on the power layers rather than narrow routing. The connector’s power pins are usually grouped to make this possible; the layout has to take advantage of the grouping rather than spreading the connections out.
The second is decoupling. The carrier holds the bulk capacitance for the module’s transient demand, and the placement of that capacitance along the current path determines whether the module sees the droop that the switching activity produces. Bulk capacitance at the point of entry, distributed capacitance near the connector, and short, low-inductance connections between them are the standard arrangement.
The third is inrush and sequencing. Modules commonly require the rails to come up in a specific order, and the carrier is where that sequence is generated. That makes the power sequencing circuitry a functional block with its own layout needs — tight component placement, stable references and clean ground.
Where These Boards Are Used
The applications are those that need computing performance inside a harsh or tightly constrained package.
Industrial automation uses them where performance is required in a limited space; medical equipment values the combination of reliability and small size; transport systems use them for flexibility and dependable operation; and aerospace and defence applications take advantage of the integration density, since qualifying one module is far more practical than qualifying a bespoke processor design.
The common thread is that the product’s differentiation is not in the processor. It is in the carrier board — the connectors, the power architecture, the analogue and application circuits, and the mechanical integration. That is where the layout effort belongs, and dense serial interfaces are where that effort is spent, as this material on high-speed routing and stackup choice sets out.
FAQ
Can one carrier accept modules of different performance levels? That is the central argument for the approach. Because the interface is standardised, the carrier can be designed once and populated with a module chosen for the application, and upgraded later without a board revision.
What is the main layout risk on a carrier board? The connector escape and the high-speed pairs leaving it. Both determine the layer count, and both are decided very early, so an error there affects the entire design rather than one interface.
Does the carrier need its own thermal design? Yes. The module dissipates its heat through a defined path and the carrier is part of it. Copper area, stiffeners and the connection into the enclosure all influence whether the module runs at its rated performance in the field.
