Differential Impedance Design Guide for Two- to Six-Layer Stackups

Differential impedance is a fabrication requirement disguised as a layout preference. The traces on the screen are only a proposal; what the receiver sees depends on the dielectric, the copper thickness and what the etcher actually produces. Agreeing on numbers before release is what keeps a design from arriving at the fabricator with an impedance target and a geometry that cannot meet it.

The recommendations below assume FR-4 with a dielectric constant of 4.4, board thickness of 1.6 mm, one-ounce copper and a solder mask with a dielectric constant near 3.5. Change any of those and the geometry must be recalculated.

What Sets Differential Impedance

A differential pair has two modes of propagation. Each trace has a single-ended impedance to its reference plane, and the pair has a differential impedance that depends on the coupling between the two traces. Bringing the traces closer lowers differential impedance; moving them apart raises it toward twice the single-ended value.

Four variables do most of the work: trace width, edge-to-edge spacing, dielectric thickness to the reference plane, and the dielectric constant. Copper thickness and solder mask coverage add a small second-order effect. This is why a pair copied from a different stackup rarely produces the same controlled impedance.

Two-Layer Boards: 100 Ohm and 90 Ohm

On a two-layer board the pair runs as microstrip over the opposite copper, and the reference plane must be continuous. For a 100 ohm differential impedance target with ground shielding on both sides, a 7 / 5 / 7 mil geometry works: 7 mil traces with 5 mil edge-to-edge spacing, plus ground traces at least 20 mil wide placed 6 mil from the pair and stitched with vias every 400 mil.

Without shielding, the same 100 ohm target needs a 10 / 5 / 10 mil geometry, and the spacing between adjacent pairs must stay at 20 mil or more, never below 10 mil. For a 90 ohm impedance target the shielded geometry is 10 / 5 / 10 mil and the unshielded version is 16 / 5 / 16 mil.

Shielding is preferred when the pair is long or the ground plane has gaps. It also costs board area, so short runs over a solid plane can safely use the unshielded geometry as long as the pair-to-pair clearance is respected.

Four-Layer Boards

With a four-layer stackup, the pair usually runs as microstrip on the outer layer over an adjacent plane. A 100 ohm differential impedance target is met with 5 / 7 / 5 mil, and adjacent pairs should be separated by at least 14 mil, which is the 3W rule applied to the pair width.

For a 90 ohm impedance target, a 6 / 6 / 6 mil geometry is typical with 12 mil pair-to-pair clearance. Where the pair runs a long distance, shielding both sides with ground at 6 mil spacing reduces radiated emissions, and the width and spacing inside the pair stay unchanged whether or not the shield is present.

Six-Layer Boards and Inner-Layer Routing

On a six-layer board the outer layers behave like the four-layer case, because the reference plane is still the adjacent layer. Routing on inner layers changes the picture: the trace is now stripline, buried between two planes, so the same differential impedance requires narrower traces, roughly one to two mils less for each of the standard geometries.

The symmetrical dielectric environment also lowers radiation and reduces sensitivity to nearby traces. That is why clock and high-speed data buses are often moved to inner layers even when board area is available on the surface.

Stackup Parameters to Document

Every impedance-controlled design should carry a stackup table: layer function, material, dielectric thickness and copper weight. For a four-layer board built from prepreg 2116 in the 4.0 to 5.0 mil range with a dielectric constant near 4.3, the table plus the target impedance gives the fabricator everything needed to build coupons.

Solder mask is part of the table. A 0.6 mil mask with a dielectric constant near 3.5 slightly reduces the impedance of microstrip, an effect that matters most on thin traces and tight spacing.

Routing Discipline Around the Pair

A controlled impedance target is only meaningful if the pair is routed consistently. Length matching should be done inside the pair, with any serpentine added symmetrically so both traces see similar coupling. Symmetry matters more than absolute length on short runs.

Avoid vias inside the pair where possible, and when a via is required, change both traces together with identical via geometry. A single via on one leg creates an impedance discontinuity and a mode conversion that shows up as common-mode noise on the cable.

The reference plane must be continuous under the whole length of the pair. Crossing a plane split forces the return current to detour, and the resulting loop radiates. Where a split is unavoidable, stitching capacitors or a deliberate plane bridge keep the return path short.

Verifying Impedance After Fabrication

Fabricators verify controlled impedance with coupons built on the same panel. A time-domain reflectometer measures the coupon and reports the value; the result should fall inside the stated tolerance, typically plus or minus ten percent. Ask for the coupon report with the shipment.

If the measured value drifts, the fix is usually in the process rather than the design. Etch compensation, lamination pressure and dielectric thickness variation are the common causes. Adjusting the design to compensate for a process that is out of control only moves the problem to the next order.

Which Nets Need Impedance Control

Not every trace needs a controlled impedance target, and over-specifying slows the layout without improving performance. The nets that need attention are those whose rise time is short compared with the round-trip delay of the trace, and those that leave the board through a cable or connector.

In practice this means USB, HDMI, Ethernet, PCIe, memory buses, clock lines above roughly 50 MHz, and any analog RF path. Short stubs to a test point or a slow control line can be routed to ordinary rules. Listing the controlled nets explicitly on the fabrication drawing keeps the fabricator focused on the geometries that matter.

Practical Ordering of Decisions

Decide the stackup first, then the geometry, then the routing rules. Fixing the geometry before the stackup is agreed produces numbers that cannot be built. Once the stackup is fixed, the impedance target becomes a constraint on width and spacing that the layout can follow consistently.

Finally, document the target on the fabrication drawing and list which nets are impedance controlled. An impedance target with no net list attached is a number the fabricator cannot act on.

FAQ

Does a differential pair need a ground plane directly underneath? Yes, on microstrip layers the plane provides the return path and defines the impedance. A gap under the pair changes the impedance and forces return current to detour, so the plane must be solid for the full length.

How much does spacing inside the pair change the impedance? Moving the traces closer together lowers differential impedance quickly; a change of a few mils at tight spacing is worth several ohms. Once the spacing exceeds roughly three times the dielectric height, the effect flattens out.

Can I use the same geometry on a thicker board? No. Increasing dielectric thickness to the reference plane raises impedance, so trace width must increase to compensate. Recalculate the stackup whenever board thickness or layer arrangement changes.

See also microstrip and stripline routing and high-frequency data bus routing.