What HDI Inspection Standards Actually Check

A high density interconnect board cannot be judged by the same inspection criteria as a conventional multilayer board. The features are smaller, the layers are thinner, and the critical defects are hidden inside the build-up structure where a visual check cannot reach them. An HDI inspection specification therefore covers three areas: appearance, structural integrity, and reliability, with the last two carrying most of the risk.

For a purchaser, understanding what those standards contain is the difference between receiving boards that work and receiving boards that pass an incoming inspection and fail in the field. For a designer, it determines what has to be stated in the fabrication drawing for the inspection to be meaningful, because a requirement that is not stated cannot be verified.

What Is Inspected on an HDI Board

The visible characteristics are checked against the general acceptance standard for printed boards, which defines acceptable, conditionally acceptable and rejectable conditions for the copper, the solder mask and the finish. On an HDI board the fine line conductors are also measured: conductor width and spacing tolerances are tighter than on a conventional board, and the registration between layers is verified because a build-up layer can be offset relative to the core beneath it.

The build-up material itself is part of the inspection. The dielectric thickness of each layer affects the impedance of the traces above it, so thickness is verified rather than assumed, and the properties that determine high frequency behaviour are confirmed against the material specification. Solder mask registration receives extra attention, because a small misalignment that would be a minor issue on a coarse pattern can expose a fine line pitch or partially cover a pad.

The Microvia Requirements

The microvia is the feature that distinguishes HDI inspection from conventional practice. The specification addresses the diameter of the via at the surface and at the target land, the thickness of the copper on the wall, the presence of voids in a filled via, and the depth of the dimple left by the filling process. It also addresses the capture pad diameter, since the registration margin between the via and the pad beneath it determines whether the connection is reliable.

Fill quality is verified by cross-section on a sample and increasingly by X-ray inspection across the panel. A void inside a filled via may pass an electrical test at room temperature and fail during thermal cycling, which is why the acceptance criteria are written in terms of the void size and position rather than of continuity alone. Where vias are stacked, the profile of the lower via becomes critical, because the upper via inherits any defect in the surface it is built upon.

Reliability Testing of the Build-Up Structure

The tests that follow inspection are designed to accelerate the failure modes the build-up structure is prone to. Thermal shock subjects the board to rapid temperature changes and stresses the plating and the filled vias through differential expansion. An interconnect stress test passes a current through a chain of vias and monitors the resistance, which detects an incipient barrel crack earlier than a functional test. Conductive anodic filament testing applies bias in a humid environment to check whether copper can migrate through the dielectric between adjacent conductors.

Reflow simulation, sometimes called preconditioning, is applied before those tests to represent the thermal exposure the board sees during assembly. A microvia that survives the reliability test without preconditioning may fail after it, because the assembly process itself is the first thermal stress the structure experiences. Where the product is intended for automotive or industrial use, the tests are extended to cover the full temperature range and a longer duration.

<img src="https://www.gopcba.com/wp-content/uploads/2026/06/Telecommunications-Electronics.jpg" alt="Thermal shock test coupon used for microvia reliability” />

What the Fabrication Drawing Should State

Inspection is only meaningful against stated requirements. The drawing should define the stackup with the material and thickness of each layer, the impedance targets and the layers they apply to, the via types with their diameters and the fill requirement, the copper weight of each layer, the surface finish, and the acceptance standard to be applied. It should also require test coupons that allow the microvia structure, the plating thickness and the impedance to be measured on the production panel.

The general fabrication sequence that produces these features is described in PCB manufacturing processes, and the dimensional limits that apply are collected in PCB manufacturing tolerances. Keeping the acceptance criteria and the quality metrics consistent between design, fabrication and incoming inspection is what makes yield and quality control predictable across production lots.

Incoming Inspection for the Purchaser

A purchaser receiving HDI boards should verify the features that cannot be recovered later. Electrical test for open and short circuits is performed on every board, but it does not detect a marginal via, so the incoming inspection should rely on the supplier’s cross-section and reliability data for each lot and confirm that those records correspond to the boards delivered. Dimensional checks on the surface, solder mask registration and finish thickness can be performed on samples.

Where a lot is critical, a sample can be cross-sectioned by the purchaser as an independent confirmation. The cost of that check is small compared with the cost of discovering a systematic plating problem after the assemblies have been built, which is why the acceptance criteria and the sampling plan belong in the purchase specification rather than in a conversation after delivery. The wider construction options are described in high density interconnect design.

Tolerances That Decide Yield

Two dimensional tolerances do more to determine the yield of an HDI board than any other factor. The first is conductor width tolerance, which on a fine line layer has to be held tightly enough that the specified impedance is achieved after etching. A line that is consistently narrower than nominal increases resistance and impedance, and a line that is wider reduces both, so the tolerance is a condition of the electrical design rather than a cosmetic requirement.

The second is registration between layers. The capture pad of a microvia is sized to absorb the offset between the via and the layer beneath it, and the accumulated registration error of a multi-stage build-up consumes that allowance. Where the tolerance is at the edge of the process capability, an occasional via lands partially outside its pad, which passes electrical test when the connection is still made and becomes a reliability risk later. The general dimensional limits that apply to these features are collected in PCB manufacturing tolerances.

Both tolerances should be quoted as values rather than implied by a general note, because the fabricator will otherwise apply the default tolerance for the process and the electrical design may not be met.

FAQ

Does an electrical test prove an HDI board is good? No. It confirms continuity and isolation. A via with a void or a thin barrel wall can pass and still fail during thermal cycling, which is why cross-section and reliability data are part of the acceptance criteria.

How large a void is acceptable in a filled via? The value is defined by the applicable specification and by the application. What matters is that the criterion is stated in the drawing, measured on a sample, and applied consistently between lots.

Why is reflow simulation part of qualification? Because assembly is the first thermal stress the board experiences. Testing without it omits the exposure that most often reveals a marginal plating or fill condition.