Designing Boards for High Performance IC Devices

A high performance IC asks more of its board than any other part on the assembly. Its core current steps in nanoseconds, its memory interface runs on a parallel bus with hundreds of synchronous lines, and its supply rails have impedance requirements that extend well into the megahertz range. A schematic that connects the pins correctly can still produce a board that will not run at speed.

The design work follows from three questions. How the power is delivered across the whole band of frequencies the device uses, how the return paths are arranged under the package, and how the thermal load leaves the die. Each of them is decided by the stackup and the floorplan long before the first net is routed.

Floorplanning Around the Package

Floorplanning starts at the device and works outwards. The memory devices, the clock source and the high speed interfaces belong close to the pins that serve them, because the length of those connections sets the timing budget. Anything that can tolerate a longer path, such as a debug header or a status LED, belongs at the edge.

The pinout of the package often constrains this more than the schematic does. Power and ground pins are distributed around the perimeter precisely so that the current can be delivered everywhere at once, and the floorplan should follow that distribution rather than concentrating all the copper in one corner of the device.

Power Integrity and the Decoupling Network

Power integrity is the requirement that the voltage at the die stays inside its tolerance no matter how fast the current changes. The decoupling network is the tool: a set of capacitors of different values, each covering part of the frequency range, connected to the device with as little impedance as possible.

The capacitor value matters less than the loop it makes with the plane. A small part placed next to the pin, with a short connection to the plane beneath, does more than a large part placed a centimetre away. Grouping the values by frequency and placing them in order of distance from the pin is the practical approach.

Plane Design for a Fast Device

A power plane works as a distributed capacitor against the ground plane beneath it, and the thinner the dielectric between them, the higher the capacitance per unit area. That is why a thin core between power and ground is worth choosing at the stackup stage for a board that carries a large digital device.

The plane pair also carries the return current for every signal that references it. Where a plane is cut by a via field or by a slot, the current has to detour, which raises the inductance locally and creates a discontinuity. Slots in a reference plane under a fast device are one of the few layout errors that no decoupling capacitor can repair.

Stackup Design and Reference Layers

The stackup design determines how many clean references are available and how far apart the signal layers are. A common arrangement pairs each signal layer with an adjacent plane, so that every net has a continuous reference within a few thousandths of an inch. The alternative, two signal layers between two planes, couples them to each other as well.

With a thicker overall board the distance between the surface layers and the planes increases, which raises the via stub length and lowers the frequency at which the stub resonance appears. Back drilling or a different layer assignment is the answer, and the trade off is described in the discussion of back drilling on high speed boards.

Interconnect Between Devices

The buses between the device and its memory are the nets that set the routing rules. A parallel bus with a common clock has to be length matched within a window, routed over a continuous reference plane and kept clear of anything that would change its impedance along the way.

The window is derived from the timing budget, not from a rule of thumb. Once the flight time difference and the setup and hold requirements are known, the allowed length skew follows, and it is often larger than the default rules suggest, which can save a great deal of routing effort on a dense board.

Thermal Path and Mechanical Support

A large package dissipates its heat through the solder balls, so the thermal path starts at the pads. A ground plane directly beneath the device spreads that heat, and a grid of thermal vias through the board carries it to copper on the other side, where it can be transferred to the enclosure.

The same package also imposes mechanical loads on the assembly. A large body on a thin board will bow when the assembly cools, and the outlying balls of the array take the strain. The stiffness of the board thickness and the arrangement of the ground planes are the design’s contribution to keeping that joint reliable.

Prototype and Bring Up

The first article of a board like this is expensive, so the design should make it easy to learn from. Test points on every rail, spare vias on the buses and a clear separation between the sections that can be isolated and measured turn a board that does not run into a board whose failure can be located.

Where the design allows, one or two spare gates or an uncommitted footprint cost little and can rescue a prototype that is otherwise complete. This is also the stage at which a supplier will tell you whether the copper weights and the via structures in the stackup are achievable, which is the same conversation described in the guidance on design release.

Clock Distribution and Reference Quality

The clock is the signal that every other timing decision is measured against, so its distribution deserves to be treated as a design problem in its own right. A single source driving several devices should be routed as a matched tree rather than as a daisy chain, and each branch should see the same load and the same reference plane along its length.

Where the device has an internal clock multiplier, the reference that feeds it sets the jitter of everything downstream. Keeping that reference short, screened and away from switching nodes is more valuable than adding a second oscillator, and the same argument applies to any analog reference that the device uses to set its own timing.

Memory Bus Skew and Termination

A parallel bus is routed as a group, with the clock or strobe as the reference for the whole group. The skew between any line and its reference has to stay inside the timing window, and the window is calculated from the device setup and hold times rather than taken from a generic rule.

Termination is the other half of the bus design. Where the driver cannot match the line, a resistor at the end of each net absorbs the reflection, and its placement relative to the receiving pin determines how well it works. The value follows from the line impedance, which in turn follows from the trace geometry and the stackup chosen earlier.

FAQ

How many decoupling capacitors does a large device need? Enough to cover the frequency range, placed where the loop inductance is low. The count follows from the current profile and the plane impedance, not from a fixed number per pin.

Does a high performance IC always need a thin core? For a device with a fast current step, a thin dielectric between power and ground adds useful high frequency capacitance and is usually worth the cost.

Can a board like this be laid out on six layers? Sometimes, if the interfaces are modest and the device has a wide pin pitch. Once a parallel memory bus is involved, the reference layers and the routing channels usually demand more.