When Layout Decisions Become Signal Integrity Problems
A schematic can be complete, correct and fully verified, and the board built from it can still fail at the first eye measurement. The reason is that a schematic describes connectivity, not geometry. It does not say which layer a net travels on, where its return current flows, what type of via carries the signal between layers, or what dielectric the board is made from. Those are all layout decisions, and at high frequency they decide whether the signal arrives intact or arrives degraded.
That distinction matters because layout choices are usually made by default. The design tool offers a via, so a via is placed. The previous project used a certain laminate, so the same laminate is reused. The signals are then routed with care, and the resulting channel is limited by decisions that were never analysed. Treating those three areas as explicit design decisions, rather than as default settings, is what separates a working high-speed layout from a hopeful one.
Decision One: Routing Topology and the Return Path
Every signal is a loop, and the current that returns to the source is part of the circuit whether or not it appears on the schematic. At low frequency the return current spreads out and takes the lowest-resistance path. As the edge rate rises, it concentrates directly beneath the trace, in the reference plane, because that path minimises the loop inductance. The routing topology you choose therefore decides the quality of a path the schematic never drew.
Any interruption of that reference turns into a detour. A slot or split in the plane, a voided region under a connector, or a transition from one reference plane to another forces the return current around the obstacle, enlarging the loop area. The consequences appear as radiated emissions, added crosstalk and degraded edges. When a signal must change reference planes, place a stitching via or capacitor next to the transition so the return path has a short way to follow.
Decision Two: Via Strategy and Stub Resonance
A through via that carries a signal from the top layer to an inner layer leaves an unused tail, or stub, below the exit point. That stub behaves as a resonant structure. Its geometry, including pad size, antipad diameter and the distance to nearby ground vias, sets the frequency at which it resonates. At resonance the stub couples energy into the surrounding planes instead of passing it along the channel, so the loss seen by the receiver rises sharply.
Published full-wave analysis of a 37.8 mil stub places its resonance at roughly 10 GHz, with around 62 percent of the signal power coupled into the surrounding planes rather than delivered. The familiar quarter-wave formula only approximates this because parasitic capacitance and inductance shift the actual resonance, often by several gigahertz. The practical rule is simple: if the signal bandwidth approaches the stub resonance, the stub must be shortened or removed, which is exactly what blind, buried and back-drilled vias do. A blind via from layer one to layer three has no stub below layer three, and back-drilling physically removes the unused barrel after plating.
Decision Three: Stackup Material Sets Speed and Loss
Two material properties dominate the electrical behaviour of a stackup: the dielectric constant, which controls propagation velocity and impedance, and the dissipation factor, which controls how much energy the dielectric absorbs. Standard FR-4 sits near a dielectric constant of 4.0 with a dissipation factor between about 0.015 and 0.025, which is adequate for signals up to a few gigahertz. Low-loss laminates reach a dissipation factor near 0.007 and a dielectric constant around 3.6, which extends usable bandwidth well beyond that.
The trap is that changing material changes impedance. Move from FR-4 to a lower dielectric constant laminate with the same trace geometry and the characteristic impedance shifts, so trace widths and dielectric thicknesses must be recalculated rather than reused. Dielectric constant also influences crosstalk, because a lower value reduces coupling between adjacent traces; the effect is strongest where long parallel runs can be shortened at the same time. These are the reasons stackup material belongs in the same decision list as routing and vias, not in a purchasing discussion at the end of the project.
Layout Decisions, Not Schematic Decisions
None of the three decisions above appears on a schematic. A schematic does not choose a via type, a layer transition or a laminate, yet those choices determine whether the signal arrives intact or arrives with its edges rounded and its amplitude reduced. Routing topology sets the quality of the return path, the via strategy sets the frequency ceiling of the channel, and the stackup material sets the loss floor and the crosstalk baseline. Signal integrity is therefore a layout outcome, not a schematic property.
Via stub resonance deserves particular attention because it is invisible in a two-dimensional view. The stackup drawing looks identical whether a via is a full through hole or a back-drilled one, and the difference only appears when the channel is analysed. The same applies to a reference-plane change: the copper looks continuous until the return current is traced at the frequency of interest.
Building These Decisions Into the Flow
The practical method is to analyse before release rather than to measure after assembly. Extract the routing topology and check the return path, particularly at every layer transition and connector. Compare via options against the bandwidth of each interface and choose the least expensive structure that keeps the stub resonance above the signal band. Simulate the stackup with the real material properties so that microstrip and stripline impedances are calculated on the actual dielectric, not on a nominal value.
Measurements then confirm the analysis. Compare insertion loss and impedance to the budget and to the simulation, and feed the difference back into the model. Return current behaviour, especially where planes are fragmented, is closely related to the effects described in ground current and harmonic distortion, and the layer transitions that create it are easier to avoid than to repair. The layer count and plane arrangement that support these choices are covered in multilayer PCB advantages for high speed.
Where the Loss Budget Comes From
A channel budget is only useful when it is written down before routing starts. Add up the loss of the package, the connector, the traces, the vias and the receiver equalisation margin, then compare the total with what the standard allows. For a 112G PAM4 link, the specification limits insertion loss at the Nyquist frequency to 28 dB, which leaves very little room for optimistic assumptions about vias and laminate.
Once the budget exists, each layout decision has a number to answer to. A stub that resonates inside the band consumes margin that the trace cannot recover. A reference change without stitching vias adds loss and radiation that no equaliser can undo. A laminate chosen for cost rather than loss quickly becomes the dominant term. Reviewing the numbers after every significant layout change is faster than discovering the problem in a compliance test.
FAQ
Can a schematic review catch these problems? No. A schematic review verifies connectivity, part selection and net naming. Return paths, via stubs and dielectric properties only exist once geometry is assigned, so they must be reviewed in the layout and verified by simulation.
When is a low-loss laminate actually necessary? When the required data rate and trace length push total channel loss beyond budget with standard FR-4. For short runs at moderate rates, FR-4 remains adequate and the money is better spent on stackup and via discipline.
What is the cheapest way to raise a channel bandwidth ceiling? Remove stubs before changing anything else. Back-drilling or moving to blind and buried vias usually costs less than switching laminate, and it can recover several gigahertz of usable bandwidth.
