Schematic Entry Mistakes That Break the Netlist

The schematic is the source of truth for the whole project. Every net in the layout, every entry in the bill of materials and every test point in the netlist comes from it, so a small inconsistency at the schematic stage propagates into the board and is much harder to find there.

Most of the errors that reach a layout are not exotic. They are duplicate net labels, a symbol with the wrong pin numbering, a part that never got a reference designator, or a rule that was accepted as a warning and never read. This article covers the ones that appear most often and what to do about them.

Why Schematic Errors Reach the Board

A schematic can be electrically complete and still be wrong. If two wires meet at a junction the tool accepts them, and if a label is duplicated the tool may accept that as well. The board then inherits a net that is connected to something the designer did not intend, and because the layout looks reasonable, nothing appears wrong until the board is tested.

The reason these errors survive is that they are mostly warnings rather than failures. A missing pin, a duplicated label or an unconnected input produces a message that can be dismissed, and in a long session it is easy to dismiss a real one among many. Treating the warning list as a to-do list rather than as noise is the single most effective habit in schematic entry.

Electrical Rule Check Warnings Worth Reading

An ERC warning about an unconnected input is the most common of all, and it is often legitimate: a spare gate left unused, an enable pin tied off internally, or test points that are not connected to anything. What matters is that each one is acknowledged deliberately. A pin that is left floating by accident will behave unpredictably, and it is far cheaper to find at the schematic stage.

The second family of warnings comes from symbol attributes. A pin that has been defined as an output and then connected to another output will be flagged, which is useful in a simulation but can be noise in a design that will not be simulated. The practical approach is to remove the input and output attributes from symbols that are never simulated, so that the warnings that remain are meaningful.

Multiple Net Identifiers and Hierarchical Designs

The multiple net identifier warning usually means one of two things: two different labels have been applied to the same wire, or two different nets have been joined by a wire that was not intended. Either way the netlist is wrong, and the fix is to find the actual location rather than to accept the warning.

In a single-sheet design the offending location is usually close to where the warning points. In a hierarchical design it is not: the conflicting label is often in a sub-sheet, and the tool reports it at the parent level. This is the main reason a hierarchical schematic deserves a deliberate naming convention, where each sheet’s nets are named after the function they serve, so that a duplicate label is obvious by inspection.

Pin Number and Footprint Mismatches

The classic failure in this category is a device whose symbol pin numbers do not match the footprint pad numbers. A transistor drawn with pins named for its terminals rather than numbered will not transfer to a footprint that expects numbers, and the connection ends up on the wrong pad. The same applies to diodes and to any part with a package that has a non-obvious numbering scheme.

The symptom appears when the netlist is loaded and the tool cannot find a pad for a net. The fix is at the symbol, not at the layout: the symbol pin numbers must match the package drawing exactly, including any pin that is unused or internally connected. Checking this once per part, when the symbol is created, avoids repeating the problem on every board that uses it.

Reference Designators and Multi-Part Symbols

A schematic that passes these checks is the first step towards a design that is consistent in quality from schematic to finished board.

Reference designators must be unique and each component must be annotated before the netlist is generated. A duplicated designator, or a designator that was never assigned, breaks the link between the schematic and the board, and the assembly data will then place the wrong part in the wrong position.

Multi-part symbols need particular care. A device split across several symbol units shares one designator, with a suffix indicating the unit, and the units must be kept together in the schematic so the association is visible. Renumbering a design whose multi-part symbols are spread across sheets is a common way to create a mismatch that only appears when the board is assembled.

Netlist Scope and Project Structure

The netlist has to be generated for the whole project rather than for a single sheet, otherwise only part of the design transfers to the layout. This is a settings issue rather than a design error, and it is worth checking once per project: the scope should cover the entire hierarchy, and the resulting netlist should contain every component in the bill of materials.

A quick consistency check is to compare the component count in the netlist with the count in the schematic and in the bill of materials. The comparison takes a minute and it has caught more transfer problems than any other single check. When the three agree, the transfer is complete. When they do not, the difference identifies whether the problem is in the scope setting or in a symbol that was excluded from the transfer.

Defaults That Do Not Match the Process

Every tool ships with a default track width, and the default is rarely what the fabricator can produce economically. A default of ten mils is comfortable for most processes, eight is common, and anything below six begins to limit the choice of supplier. Setting the width rule from the actual process, rather than from the tool default, prevents a design that is electrically fine from being unquotable.

The same applies to clearance, via size and solder mask expansion. These are process values, and the design guidelines that keep a board manufacturable should be converted into tool rules at the start of the project. Doing it once means the design rule check catches the exceptions, instead of the fabricator catching them later. The trace width and current calculation is the other half of the same setup, since the width has to satisfy the current requirement as well as the process minimum.

FAQ

Should every electrical rule check warning be resolved? Every one should be acknowledged, which is not the same thing. A warning that reflects a deliberate decision can be accepted, but it should be recorded so that the next person does not re-investigate it.

Why does the tool report an error in one sheet when the conflict is in another? In a hierarchical design the netlist is resolved at the parent level, so a duplicate label in a sub-sheet is reported where the nets meet. Searching the sub-sheets for the label named in the message is usually the quickest route to it.

What is the most common cause of a footprint not being found? A pad numbering mismatch between the symbol and the footprint, followed by a footprint name that was changed in the library after the symbol was placed. Both are visible by comparing the netlist error with the symbol and the library part.