PCB Stack-Up Design: Layers, Planes and EMC

The stack-up is the arrangement of copper layers and dielectric between them, and it is decided once for a design. It sets the cost of the board, the impedances that can be achieved, the crosstalk between routing layers and the emissions the product will produce, and none of those can be changed later without building a different board.

This article describes how the layer count is derived from the routing and the power distribution, and the rules that govern the order in which the layers are arranged. The decisions are taken before the layout begins and they constrain everything that follows.

Why the Stack-Up Drives Cost and EMC

Adding layers makes routing easier and the product more expensive. Each additional pair of layers adds material, lamination cycles, drilling and imaging steps, and the price rises faster than the layer count, because the process becomes more difficult as well as longer.

The same arrangement controls emissions. A signal layer next to a continuous plane has a return path immediately beneath it and radiates very little; a signal layer next to another signal layer has a return path somewhere else and radiates considerably more. The stack-up is therefore the first EMC decision, taken long before any measurement is possible, and it is the cheapest place to solve an emissions problem.

Deciding the Number of Signal Layers

The starting point is the routing demand. After the placement is fixed, the areas where routing is congested are identified, and the density is estimated with the tools available: the number of connections that must cross a given region, and the space each of them needs.

Special signals are counted separately, because they consume more room than their trace width suggests. Differential pairs need their spacing held, sensitive nets need clearance from their neighbours, and impedance-controlled nets need a reference plane adjacent to the layer they run on. The number of signal layers follows from those counts rather than from the total number of nets.

Deciding the Number of Plane Layers

Plane layers are needed for each supply that has to be distributed and for the returns that go with them. A design with several rails and a requirement to keep them isolated may need more than one plane layer, and a design with a single rail and a low-speed circuit may need only one.

The requirement to keep circuits apart is what usually decides the count. Where an analogue domain and a digital domain have to be separated, each benefits from its own ground reference, and the same applies to high-current supplies, whose returns should not share copper with sensitive measurements. Multiple ground planes also lower the impedance of the reference, which is a benefit in itself.

Rules for Arranging the Layers

The first rule is that each signal layer should be adjacent to a plane. The copper of the plane provides the return path and, incidentally, a degree of shielding for the layer beside it. The second is that power and ground planes should be closely coupled, which means a thin dielectric between them, because the pair forms a capacitor that lowers the high-frequency impedance of the supply.

The third rule concerns the fast signals. Where a design has high-speed nets, they are placed on inner layers sandwiched between two planes, so that the copper above and below contains the field and the emissions are confined. The fourth is a prohibition: two signal layers should not be placed directly adjacent to each other, because the coupling between them is difficult to control and the crosstalk that results appears as a functional failure. A ground layer between them removes the problem, and the comparison of stacks from one to eight layers shows how the arrangements change as layers are added.

Common Stack-Up Arrangements

A four-layer board is usually built as signal, ground, power and signal, which gives both routing layers a plane beside them and puts the planes in the middle. This is the most cost-effective arrangement for a design of moderate complexity, and it is the one most often chosen when two layers are not enough.

A six-layer board is typically signal, ground, signal, power, ground, signal, which sandwiches the fast inner routing between the power plane and a ground plane. The same logic extends to eight layers and beyond, where additional ground layers are added to give each high-speed routing layer its own reference rather than sharing one with another domain.

Symmetry and Manufacturability

The stack should be symmetrical about its centre, in both the layer types and the dielectric thicknesses. A stack that is heavier on one side will tend to bow during lamination and during reflow, and the bowing is a mechanical problem that no routing decision can fix. Where an odd number of layers is required by the design, the imbalance has to be managed deliberately, as the notes on balanced stack-ups with an odd layer count explain.

The materials have their own constraints. The dielectric thickness available is a set of standard values, and a stack that assumes a thickness the supplier does not stock will either be rebuilt or be produced with a substituted material. Where the design depends on a specific dielectric constant, the material is named in the stack-up drawing rather than left to the fabricator.

Impedance, Material and the Coupon

Once the layer order is fixed, the trace geometry that achieves each impedance target can be calculated, because the height above the plane and the dielectric constant are known. This is the point at which the routing rules become real numbers rather than intentions.

The material also affects how much of the signal survives a long route. A stack designed for high-speed links has to consider the loss of the dielectric as well as the impedance, and where the runs are long the selection of a low-loss laminate becomes part of the stack-up decision rather than a separate one.

What to Document

The stack-up drawing is the document that the fabricator builds to, and it has to state the layer order, the copper weight on each layer, the dielectric thickness and material between them, the finished thickness and its tolerance, and the impedance targets with the layers they apply to.

Where the stack-up is notional, the fabricator will substitute, and the substitution will change the impedance and the EMC behaviour that the design was planned around. Recording the stack as a requirement is what makes the difference, and the requirements for a prototype multilayer build begin with it.

FAQ

Is more layers always better? No. Additional layers buy routing room and improved references, and they cost money. The right count is the smallest one that satisfies the routing and the EMC requirement.

Can two signal layers be adjacent if the traces cross at right angles? Crossing at right angles reduces broadside coupling compared with parallel runs, but it does not provide a return path. It is a mitigation rather than a solution.

Should the fast signals be on the outer layers or the inner ones? Inner layers, between planes, where they are shielded on both sides. The outer layers are better used for slower signals and for the components themselves.