Thermal Vias and Filled Vias: Choosing for Heat and Current

A via can be asked to do two very different jobs. It can conduct heat away from a device, or it can provide a flat surface for a component to be mounted on. The first requirement is met by an array of plated holes connected to a plane, and the second by filling the hole and plating over it.

Because both are described as vias in the same design, they are often specified with the same rules, and the result is either a thermal path that is weaker than expected or a filled via that costs more than the design needed.

The Two Purposes

A thermal via exists to move heat from the surface of the board to an internal plane or to the opposite side, where a heat sink or a chassis can absorb it. Its performance is proportional to the copper cross section, the number of vias and the area of the plane they connect to.

A filled via exists to eliminate the hole. The opening is closed with a material and then plated over, so that a component pad or a solder ball can sit on a flat surface. Its performance is measured by the planarity and by the absence of voids rather than by the copper cross section.

<img src="https://www.gopcba.com/wp-content/uploads/2026/09/Exploring-Semi-Additive-Processes-SAP-in-Ultra-HDI-PCB-Fabrication-95263.jpg" alt="Thermal via array under a power device pad” />

Anatomy of a Thermal Via Array

A thermal via is a plated hole with a thin copper wall, often 20 to 25 micrometres thick, connected at both ends to copper areas. Heat flows down the wall and into the plane beneath, and the array of many holes provides a parallel path that reduces the total thermal resistance.

The array is most effective when the vias are close to the heat source and when the plane they connect to is large. Spacing them further apart increases the spreading resistance in the copper above them, so the useful radius of an array is limited by the copper thickness rather than by the number of vias.

Filled and Capped Vias

A filled via is a plated hole that has been filled with a conductive or non conductive material and then capped with plating so that the surface is flat. Where the fill is conductive, the via also conducts heat, but through the fill material rather than through the copper wall.

The filling process is chosen from the geometry and from the required planarity. A paste fill is applied through a stencil and cured, while a plated fill closes the hole from both sides and leaves solid copper. The latter gives the best thermal performance and the highest cost.

Thermal Resistance Comparison

For a given hole diameter, a plated and copper filled via conducts heat far better than an open plated via, because the cross section is solid metal rather than a thin sleeve. A paste filled via sits between the two, depending on the conductivity of the fill.

An array of open plated vias can approach the performance of a smaller number of filled vias if there is enough area for the array. The comparison is therefore made on the total thermal resistance of the path, which includes the copper above the vias, the vias themselves and the plane beneath.

Design Rules for Arrays

Place the vias directly under the thermal pad of the device rather than around it, keep the pitch close to the limit that the fabrication process allows, and connect the vias to a copper area on the opposite side that is at least as large as the array. Where the vias cannot be placed under the device, the copper above them has to spread the heat, which requires thickness.

Where the via also carries current, the number of vias is set by the current rather than by the thermal requirement, and the two calculations are performed separately. A common error is to size an array for current and assume that the thermal performance follows.

Interaction with Assembly

An open via under a thermal pad will wick solder during reflow, which leaves voids in the joint and reduces the thermal contact. That is the main reason a via in pad design is filled and capped rather than left open, and it applies whether the thermal requirement is large or small.

The fill also affects the paste volume. A filled and planarised via presents a flat pad, so the stencil aperture can be designed as a normal pad, while an open via requires a reduced paste volume or a gasket like arrangement to prevent wicking.

Testing Thermal Performance

The performance of a thermal via structure is measured on a test vehicle: a heater and a temperature sensor are placed on the board and the temperature rise is measured at a known power. Comparing two structures on the same vehicle gives a direct measurement of the thermal resistance difference.

The measurement is repeated after thermal cycling, because a via structure can degrade if the plating cracks or if the fill separates. The change in thermal resistance is often the first indication of a reliability problem, appearing before any electrical failure.

Selection Rules

Choose an open thermal via array where the heat is moderate, the area is available and the vias are not under a solder pad. Choose a filled and capped via where the via is in a pad, where the planarity matters for assembly or where the heat flux is high enough that the array would be impractically large.

gopcb produces boards with plated thermal via arrays, conductive and non conductive fills and plated over caps with defined void limits, and can compare the thermal resistance of the options on a test vehicle before the design is committed.

Assembly and Rework Considerations

Solder wicking is the failure mode that decides most via choices under a thermal pad. When an open or unfilled via sits inside a pad, the paste reflows and solder wicking draws material down the barrel, leaving voids in the joint and an uneven surface for the component. A filled and capped via removes that path entirely, so the paste stays on the pad and the joint forms as it would on solid copper. The same argument applies to any via placed inside a pad that must carry a large thermal or current load.

Rework follows the same logic. A capped via presents a flat, repeatable surface, so a device can be removed and replaced more than once without the pad collapsing. An array of open vias tends to wick a little more solder on every reflow, and after two or three passes the joint quality is no longer predictable. Where the product will see field returns and board level repair, specifying a filled and plated over via under the thermal pad is normally cheaper than the rework it avoids.

FAQ

Can an open via be used under a thermal pad? It can, but the solder wicks into the barrel and the joint contains voids. The normal practice is to fill and cap the via so that the pad is flat and the solder stays where it is placed.

How many thermal vias are enough? Enough that the total thermal resistance meets the target, which depends on the via diameter, the plating thickness, the array area and the plane beneath. It is calculated rather than assumed.

Does a filled via conduct heat better than an open one? A copper filled via does, because the cross section is solid metal. A paste filled via depends on the fill conductivity and may be no better than a well designed array of open vias.

Related reading: copper plating and via filling, via in pad versus plated through, embedded copper coin PCB, and thermal substrate comparison.