Signal and Power Integrity Analysis for 3D IC Packages

For most of the history of integrated circuit design, a system was built from a monolithic device mounted on a package and soldered to a board, and the signal and power integrity work divided neatly along those boundaries. The chip, the package and the board were analysed separately and in sequence, with margin allocated between them. That division is now breaking down as devices are assembled by stacking multiple dies in one package.

A three dimensional integrated circuit is not a component with more pins; it is a small system in its own right. Dies are stacked vertically, connected through silicon vias and micro bumps, and the interfaces between them operate at multi-gigabit rates while sharing a power delivery network that spans the whole stack. Signal and power behaviour interact across levels, and a problem that appears at the board can originate in a die to die interface several layers above it.

Why the Sequential Method Breaks Down

In the traditional flow, the component level power requirement was analysed for the device and its package, while signal integrity was verified channel by channel, and the package and board teams worked in parallel and negotiated the split of the timing and voltage budget. Each analysis assumed a fixed boundary condition at the interface it was given, which is a reasonable approximation when the interfaces are relatively benign.

In a stacked device, the boundaries are no longer benign. The dies are physically close, so coupling mechanisms that were negligible between a package and a board become significant between adjacent dies. The power delivery network is shared across the stack, so current drawn by one die produces a voltage response at another, and the impedance of a through silicon via is part of the path. Analysing each element in isolation, with a simplified model of its neighbours, cannot capture effects that propagate through the whole assembly.

What the Stack Adds Electrically

Three structures define the electrical behaviour of the stack. The inter-die interface, which may be a wide parallel bus or a high speed serial link, sets the bandwidth that the assembly can support. The through silicon via, which carries both signal and power vertically, has resistance, capacitance and inductance that vary with its geometry and with the proximity of neighbouring vias. And the power delivery network, which spans the voltage regulator, the package substrate, the vias and the on-die distribution, determines the supply impedance seen by each circuit.

These structures interact. Current flowing through a via for a high speed signal creates a field that couples into vias carrying supply current, and simultaneous switching of a wide interface produces a supply disturbance that affects the timing of the interface itself. That mutual dependence is why signal integrity and power integrity are discussed together in stacked designs rather than as separate analyses.

Co-Simulation Across Die, Package and Board

The response to that interdependence is to analyse the assembly as one electrical system rather than as a sequence of separate parts. A co-simulation links the die model, the package model including its vias and traces, and the board model, so that the impedance seen by a circuit on one die includes the contribution of everything above and below it. The verification is progressive: the models are built and checked at each level, then combined, and the combined result is compared with the level-by-level analysis to confirm that the coupling effects are captured.

The practical consequence is that analysis must begin early and proceed in parallel rather than after the physical design is complete. Each participant in the ecosystem, the foundry, the assembly house and the system designer, holds part of the model, and the interfaces between them have to be defined in advance so that the models can be combined. Where that coordination is missing, the stack is assembled from parts that were each verified against a simplified boundary.

What Board Designers Can Take From It

The board is one layer of a stack that is now analysed as a whole, and the implications reach the placement and stackup decisions that a board designer controls. The power delivery network seen by the device extends from the voltage regulator through the board planes to the package and into the die, so the board’s plane impedance is part of the total and cannot be designed in isolation; the techniques are described in the power plane design guide.

Interconnect density follows. A device that presents thousands of connections in a small area requires high density construction at the board as well as in the package, and the rules that govern that construction are covered in high density interconnect design. Signal paths through the board must be analysed with the same attention to transitions as the paths inside the package, following impedance discontinuity analysis, and the thermal load of a stacked device concentrates in a smaller area than a conventional package, which changes the assumptions described in thermal management PCB design.

Thermal and Mechanical Coupling in a Stack

Stacking dies changes the thermal problem as much as the electrical one. The power dissipated by several dies is concentrated into the footprint of the smallest one in the stack, and there is no large package body to spread it. The result is that the board has to remove heat from a smaller area, which affects the copper distribution, the via arrangement and the choice of substrate. The temperature of each die also affects its electrical behaviour, so the thermal and electrical analyses are coupled in the same way that signal and power integrity are.

Mechanical reliability adds another constraint. The stack is built from materials with different expansion coefficients, and the joints that connect the dies experience stress with every temperature cycle. The board contributes to that stress through its own expansion and through the stiffness of its attachment, which is why the assembly and the board are usually qualified together rather than as independent items.

For the board designer the practical conclusion is that a stacked device is not simply a component with a high pin count. Its supply impedance, its heat load and its mechanical stress all depend on decisions made at the board level, and the analysis that supports those decisions has to start before the layout is fixed rather than after it is complete.

Progressive verification is the discipline that makes this practical: check each element on its own, combine them in stages, and compare the combined result with the individual ones so that a coupling effect is attributed to the interface that caused it rather than to the whole assembly.

FAQ

Is a 3D IC only relevant to advanced products? The extremes are, but the underlying principle is not. Any design where the supply impedance and the signal return path span more than one package boundary benefits from being analysed as one system rather than as separate blocks.

What is the most common mistake in stacked designs? Assuming that a boundary condition from the board can be used unchanged at the die interface. The intervening vias and substrate change the impedance, and a model that omits them will predict behaviour that cannot be measured.

Does a through silicon via behave like a board via? In principle yes, and in practice its geometry makes the parasitic capacitance and the coupling to neighbouring vias more significant. The modelling has to include the surrounding context rather than the via alone.