60-Layer PCB Manufacturing: What Ultra-High Layer Counts Take

In its half-year report published at the end of August 2026, a Chinese board manufacturer disclosed that it had qualified M8 and M9 grade ultra-low-loss materials, completed certification for fifty-layer technology, reached a maximum capability of sixty layers, and validated multi-order HDI production at seven plus N plus seven. The same disclosure described breakthroughs in 224 gigabit per second transmission on ultra-high-layer, ultra-low-loss boards, including deep aspect-ratio drilling, interlayer alignment and flatness control across large processor areas, with shipments planned for the second half of the year. A 60-layer PCB is the clearest measure of how far that capability race has moved.

Layer counts rise because the number of signal nets rises. An AI computing board must route hundreds of differential pairs out of a package, deliver power to components drawing hundreds of amperes, and maintain reference planes for impedance control on every high-speed layer. Each of those requirements consumes layers, and the combination pushes a board that would have been twenty layers a few years ago toward fifty or sixty.

A 60-layer PCB is not simply a thicker version of a twenty-layer board. The manufacturing problems change in kind rather than degree, and most of them are related to accumulated error across a tall stack of laminated cores.

Registration Error Accumulates Layer by Layer

Each lamination cycle moves the material slightly. Resin flows, copper expands and contracts, and the result is a small dimensional change that must be measured and compensated. On a thin board the accumulated movement stays inside the drill-to-target window. On a tall stack the errors of several sequential laminations add together.

The practical consequence is that registration competence, not layer count, defines the highest achievable stack. A factory that can hold tight registration across ten laminations can build a taller board than one that cannot, even if both own similar drilling equipment. The difference appears in yield rather than in capability statements.

Material choice interacts with this directly. A laminate with lower expansion in the X and Y directions moves less during processing, which widens the usable window. That is one reason ultra-low-loss materials are often also specified for their dimensional behaviour, not only for their electrical performance. Selecting them is a capability decision as much as an electrical one.

Another factor is panel size and handling. Thick, high-layer-count panels are heavy and less flexible, and they must be moved through many process steps without damage. Handling equipment that was adequate for thin boards may not be adequate here, and the resulting scratches and edge damage become cosmetic rejects on an expensive panel. Factories building this class of work usually invest in dedicated handling long before they invest in additional drilling capacity.

Deep Aspect-Ratio Drilling

Holes in a thick board are deep relative to their diameter. A board sixty layers thick may be over five millimetres from surface to surface while requiring holes less than a third of a millimetre across, producing an aspect ratio that challenges both drilling and plating.

Drilling such a hole straight is difficult because the bit wanders, and the entry and exit positions diverge. The machine must control spindle speed, feed rate and depth with precision, and the drill bit must be changed before wear degrades the hole wall. Entry and backing materials reduce exit burring but add their own variables.

Plating is the harder problem. Getting copper into a deep, narrow hole uniformly requires control of the plating chemistry, the flow through the hole and the current distribution. Thinner copper at the centre of a deep hole produces higher resistance and a local hot spot under load, which becomes a reliability issue rather than a yield issue. Because such a defect cannot be seen from outside, verification depends on cross-section sampling and on resistance measurement rather than on optical inspection.

Alignment Between Layers in a Tall Stack

Beyond drill registration, a tall stack requires that the internal features of each core align with the next. On a board with sixty layers, dozens of separate inner layers must register to a common datum, and each of them contributes variance. The composite alignment budget is therefore much tighter than a single layer would suggest.

Layer-to-layer alignment also affects impedance. If a signal layer shifts relative to its reference plane, the distance between them changes locally, and with it the impedance. On high-speed boards this is measurable, and it is one of the reasons impedance control on very thick boards is specified with tolerance bands rather than nominal values.

Managing alignment requires both equipment and discipline: fiducial strategy, tooling control, and measurement of alignment on production panels rather than on a first article. Factories that track alignment as a control parameter detect drift before it produces scrap, and on a sixty-layer board scrap is expensive because the material and process time are both substantial.

Thermal performance also changes with thickness. A thick board spreads heat laterally more effectively than a thin one, which helps with power delivery, but it also stores more heat and takes longer to reach equilibrium. Under sustained load, the thermal time constant matters for how the board behaves in a system with variable airflow, and it is worth modelling rather than assuming.

Flatness Across Large Device Areas

Large processor and accelerator packages require the board beneath them to be flat within tight limits, because ball grid array joints cannot tolerate a significant gap. On a thick board, flatness is difficult because the copper distribution varies across the panel and the resin moves differently in dense and sparse regions.

The design response is copper balancing, distributing copper so that the resin flows uniformly. The manufacturing response is control of lamination pressure and temperature profiles, matched to the pattern of the panel. Both are needed, and neither is sufficient alone.

Flatness is usually specified for the area beneath the device rather than for the whole board, which is a more useful requirement and easier to achieve. Specifying whole-board flatness tolerances that the application does not need raises cost without benefit, and it is one of the more common examples of an over-specified input.

Materials for 224 Gigabit Channels

Transmission at 224 gigabits per second per lane demands very low loss together with stable dielectric constant. M8 and M9 grade laminates are formulated for this, and their processing windows are narrower than standard materials. They are also more expensive and available from fewer suppliers.

Because these materials are difficult to process, they concentrate capability among factories that have already learned their behaviour. A laminate that flows differently, drills differently and expands differently from the standard product requires new process recipes, and those recipes are developed by running production rather than by reading data sheets.

Supply risk follows. A board that depends on a single M9 material from a single supplier has a schedule exposure that no manufacturing skill removes. Qualifying an alternative before volume production, and verifying that it meets both the electrical and the process requirements, is part of a responsible quality system.

Test strategy has to be adjusted as well. Probing a thick board with many layers requires access to internal nets, which usually means designing test vias into the stack. Those vias consume routing resources on every layer they cross, so they must be planned during layout rather than added afterwards, and their presence changes the impedance environment locally.

Yield Economics at the Top of the Range

The economics of very high layer counts are dominated by the cost of a scrapped panel. A sixty-layer board contains sixty layers of material, dozens of process steps and a substantial amount of machine time. When one fails at final inspection, all of that is lost, and the remaining boards in the order must carry the cost.

This makes in-process verification essential rather than optional. Checking alignment, plating thickness and hole quality at intermediate stages allows a defective panel to be removed before more value is added. Factories that only test at the end carry more risk per order, and their pricing reflects it.

It also explains why the highest layer counts command a price premium that reflects risk rather than raw material. Buyers comparing quotations on high-layer-count boards are comparing different yield assumptions, and the difference in price is usually a difference in confidence.

What Buyers Should Establish Before Committing

Three questions are worth answering before placing a high-layer-count order. What is the demonstrated yield on comparable stacks, measured over a production window rather than a campaign? How is alignment controlled and measured during the build? And what process capability exists for the specific laminate class the design requires?

Answers supported by records are far more useful than capability statements. A factory that can show alignment trend data, plating cross-sections and yield history for a similar stack is telling a buyer something concrete about risk. One that can only describe equipment is not.

Ultra-high layer counts will keep rising as computing packages grow, and the factories that can hold registration, plating quality and flatness at the same time will keep a durable advantage. For customers, engaging board manufacturing capability early, while the stack is still being defined, is the surest way to avoid discovering those limits during production. A partner who can discuss process planning alongside the stackup turns a difficult build into a predictable one.