Copper Foil Roughness and High-Frequency Insertion Loss

Loss in a high-speed channel is usually blamed on the laminate, and a change of dielectric is ordered, while the copper surface the signal actually travels on goes unexamined. Above a few gigahertz the two contributions are comparable, and the one that is easier to control is often the foil.

Why Foil Profile Matters Above a Few Gigahertz

A conductor carries current in a layer whose thickness falls as frequency rises. At one gigahertz in copper the skin depth is a little over two micrometres, and by ten gigahertz it is below one. When that layer is thinner than the peaks and valleys of the foil surface, the current has to follow the topography rather than run along a smooth plane.

The consequence is that the path length of the current is longer than the geometric length of the trace, and the effective resistance is higher than a calculation based on a smooth conductor would predict. The effect grows with frequency, so it appears as additional insertion loss that worsens toward the high end of the band rather than as a uniform attenuation.

This is why copper foil roughness moves from a fabrication detail to a design parameter once a link runs above roughly five gigabits per second, and why the same stack can measure differently when the foil is changed without any other revision.

How Skin Effect Meets Roughness

The classical treatment of skin effect assumes a plane boundary. Real foil is dendritic on the side bonded to the dielectric, because that topography is what gives the copper its grip. The treatment tooth depth on standard electrodeposited foil can exceed five micrometres, which is several times the skin depth at ten gigahertz.

Two effects follow. The first is the increase in path length already described. The second is that the current is crowded into the tips of the profile where the local field is highest, so the current distribution is no longer uniform across the width of the trace. Both raise the resistance per unit length.

The loss that results is a conductor loss, not a dielectric loss, and it cannot be fixed by choosing a lower-loss resin. It also cannot be fixed after the fact by changing trace width, because widening a trace lowers resistance only until the width is no longer small compared with the return path geometry.

Reading a Profile Number: Rz and Rq

Surface roughness is quoted in several ways and they are not interchangeable. Rz is the average of the maximum peak-to-valley heights over the sampling length, and Rq is the root mean square of the profile about the mean line. A supplier may quote either, and the numbers differ by a factor that depends on the distribution of the peaks.

What matters for modeling is a value that corresponds to the foil surface after lamination and after the oxide treatment, because the treatment that provides adhesion adds topography of its own. A profile measured on incoming foil will read lower than the same foil measured on a finished board.

Sellers of material often quote the smoothest number that can be defended. The practical approach is to ask for the measurement method, the sampling length and the point in the process at which the sample was taken, and to compare like with like.

Foil Types and Their Roughness

Standard electrodeposited foil has a treatment tooth depth measured in micrometres and is the least expensive option. It is entirely adequate for digital designs up to a few gigabits per second and for essentially all analog and power work.

Rolled and annealed foil is smooth on both faces and was historically used for flexible circuits and for high-frequency work, but it is more expensive and harder to handle in thin gauges. Its roughness is low enough that conductor loss from profile is negligible over the bands used in most microwave work.

Very low profile foil, commonly called VLP, and hyper very low profile foil, abbreviated HVLP, are electrodeposited products whose treatment has been engineered to provide adhesion with less tooth. HVLP foil is now the default choice for links above ten gigabits per second where the stack is otherwise conventional.

The Adhesion Trade-off

The reason standard foil has a rough treatment is that mechanical interlocking is what holds it to the resin. A smoother foil depends more on chemical bonding between the treatment and the resin system, and the bond is more sensitive to the quality of the lamination cycle.

The practical consequence is that a switch to HVLP foil should be accompanied by attention to the lamination profile and to the oxide chemistry, and it should be evaluated with peel strength measurements rather than assumed to behave like the foil it replaced. A laminate supplier and a fabricator who have qualified the combination will have that data.

Where a design uses a very smooth foil with a resin system that was not qualified for it, the failure mode is not a loss of signal but a delamination that appears after thermal cycling, which is far more expensive to diagnose.

Conductor Loss and Dielectric Loss Together

The total attenuation of a stripline or microstrip is the sum of the conductor term and the dielectric term. The dielectric term rises linearly with frequency and is set by the dissipation factor of the laminate. The conductor term rises with the square root of frequency for a smooth conductor and faster once roughness is taken into account.

Because the two have different frequency dependence, the crossover point depends on the stack. In a thin, low-loss laminate the conductor term can dominate over much of the band, which is why changing to a lower dissipation factor resin sometimes produces less improvement than the data sheet suggests.

A useful discipline is to compute both terms for the intended stack before selecting material. Our high frequency laminate notes and the laminate material properties summary give the parameters needed for that estimate.

Modeling Roughness: Correction Factors

Field solvers handle roughness through a correction factor applied to the conductor term. The better known models express the factor as a function of the ratio of roughness to skin depth, and they differ substantially at high frequency, which is why two simulations of the same stack can disagree.

The models were fitted to particular foil types and particular measurement setups, so a factor calibrated for one supplier’s foil may overstate or understate the loss for another. Where the budget is tight, the reliable approach is to correlate the model against a measured coupon from the same fabricator.

Fitting the model to a measurement on the actual stack turns the roughness question from a debate into a calibration constant, and it makes subsequent predictions trustworthy for similar geometries.

Stack-up Decisions That Reduce Loss

The strongest lever available to the designer is the position of the trace in the stack. A stripline buried between two reference planes confines the field in the dielectric, and the conductor surfaces that matter are the two faces of the trace, not the outer surface of the board where plating and soldermask add losses.

Using the same foil on both sides of a symmetric stack also keeps the two conductors matched, which matters for differential pairs where a difference in loss between the legs converts part of the differential signal into common mode.

Where the stack cannot be changed, routing the critical link on an inner layer with a thin dielectric to the reference plane spreads the field and reduces the proportion of energy in the conductor, at the cost of a wider trace.

What the Fabricator Controls

The fabricator controls the foil selection, the lamination cycle, the oxide treatment and the plating. Plating adds copper to the surface and slightly modifies the profile, and the amount of it that reaches the trace side depends on the process. Our plating thickness notes describe the control points.

Etching also matters. An over-etched trace has a trapezoidal cross section with a narrower top, and the reduction in cross sectional area raises resistance. Our etching process notes cover the trade between etch time and profile.

Because both plating and etching move the effective roughness, the useful specification is a measured loss on a coupon of the final stack rather than an incoming foil profile.

Measuring Loss on a Coupon

A coupon carrying a known length of the critical geometry, measured with a vector network analyzer, gives the attenuation per unit length directly. Comparing two coupons from different lots detects a process shift, and comparing a coupon with a length of the production trace gives a sanity check that is independent of any model.

The coupon should be built on the same panel as the production circuit and should carry the same foil, the same resin and the same plating, because those are the variables being controlled. A coupon built separately controls nothing.

Keeping the coupon data with the lot records also makes the measurement valuable later. A field report of excessive loss can be compared against the coupon data for the same date code, and a supplier discussion becomes a technical comparison rather than an exchange of opinions.

When Roughness Does Not Matter

Below a few hundred megabits per second, and over short distances even at higher rates, the conductor term is small enough that the extra cost of a smooth foil buys nothing. The right answer for a control board or a power supply is standard foil, and specifying HVLP there consumes budget that would be better spent on impedance control.

It also does not help where the loss budget is dominated by a connector, a cable or a package. In that case reducing board loss by a fraction of a decibel changes the link margin by an amount that cannot be measured, while the connector transition often accounts for several decibels.

Roughness also becomes irrelevant when the channel equalization or the forward error correction has enough headroom to absorb the loss. Where the link works with margin, the honest conclusion is that no change is needed.

Specifying Foil on the Fabrication Drawing

When the foil matters, name it. A note giving the foil type, the profile specification and the measurement point removes an ambiguity that a fabricator would otherwise resolve by substituting a lower cost equivalent.

State also whether the foil applies to both copper layers of a symmetric pair, and whether the copper weight is a nominal value before or after plating. Vague notes about smooth copper are ignored, and reasonably so, because they describe an intention rather than a requirement.

If the loss is important enough to be specified, it is important enough to be verified. Requiring a coupon measurement and a record of the result is the only way to know that the note was honored, and it costs far less than discovering the substitution during qualification.

FAQ

Does HVLP foil reduce loss noticeably? Above ten gigabits per second the improvement over standard foil is often measurable as a fraction of a decibel per inch, which matters over a backplane and matters little over a short link.

Can roughness be improved after fabrication? No. The topography is set by the foil and the bonding treatment, and no subsequent process smooths it. Selection happens at the start of the program.

What does gopcb provide for a loss-sensitive build? We provide foil options with their profile data, coupons built on the production panels, attenuation measurements from those coupons and the lot records that tie them together. Where a stack must be qualified, we build and measure before the program commits to volume.