4-Layer PCB Design: Stackup, Placement and Routing Steps
Four layers is the point where a board stops behaving like a flat piece of copper foil and starts behaving like a transmission system. It is also the layer count where most products find their best balance of cost, routing freedom and electrical performance, which is why so many industrial and consumer designs settle there. This 4-layer PCB design guide walks through the design process in the order the decisions actually have to be made.
What a 4-Layer Stackup Gives You
The classic construction places signal routing on the outer layers and dedicates the two inner layers to power and ground. That arrangement gives every signal a nearby reference, which controls impedance and provides a short return path for the current that flows back to its source.
The practical benefits show up as lower radiated emission, better signal integrity on medium-speed interfaces, and much less congestion on the routing layers. Compared with a two-layer board, the inner layers absorb the power distribution problem that otherwise consumes a large share of the available copper.
Step 1: Define the Electrical Requirement
Start with the numbers, not the tool. Note the supply voltages and their tolerances, the maximum current each rail must carry, the fastest signal edge rate, and any interface with an impedance requirement such as USB, Ethernet or a differential pair that must hold 90 or 100 ohms.
Then write down the physical constraints. Board outline, mounting holes, connector positions and the height available above and below the board all influence placement before a single component is moved. Thermal constraints belong on the same list, because a power device that cannot shed heat will force a layout change later.
Step 2: Plan the Stackup and Thickness
Choose the finished thickness and the dielectric spacing early, because they set trace width for any given impedance. A typical four-layer build uses around 0.5 mm between the outer layer and the adjacent plane and a similar spacing between the two inner layers, though the exact values depend on the fabricator’s standard construction.
Confirm the impedance targets against a real stackup before routing. Calculate the trace width for each target using the fabricator’s dielectric thickness and copper weight, and record the result. Discovering that a 50 ohm trace needs a width the assembly cannot support is a problem best found in a calculator rather than a layout.
Step 3: Schematic and Netlist Discipline
The schematic defines connectivity, and the layout only realises it. Net naming is worth a few minutes of attention: power nets, ground nets and differential pairs should be named so that they can be identified at a glance in the layout tool. Anonymous names such as N$127 create errors that survive review because nobody can see what they are.
Run the electrical rule check and clear every warning rather than suppressing it. A missing power pin or an unconnected enable line produces a board that fails on the bench, and the cost of finding it after fabrication is measured in weeks.
Step 4: Component Placement Drives Everything
Placement determines whether the routing will be easy or impossible. Start with the parts that cannot move: connectors at the board edge, mounting holes, switches and any display or sensor with a defined position. Then place the large devices and the power conversion stages, keeping the switching loop compact.
Group components by function so that the associated traces stay short. Decoupling capacitors belong next to the pin they serve, not in a tidy row somewhere else on the board. Keep noisy circuits such as switching regulators and crystal oscillators away from sensitive analog sections and from the board edge where they radiate most effectively.
Leave room for thermal relief. Components that dissipate power need copper area, vias down to the ground plane and clearance from heat-sensitive parts. That is a placement decision, not a routing one.
<img src="https://www.gopcba.com/wp-content/uploads/2026/09/222-1.jpg" alt="Design rule check passing on a routed four layer PCB layout” />
Step 5: Power Plane and Ground Plane Assignment
Assign one inner layer as the ground plane and keep it as continuous as possible. The ground plane is the reference for every signal on the board, so every split, slot or isolated island degrades the return path somewhere else. Where a split is genuinely needed, keep the two regions connected at a single point and never route a signal across the gap.
The power plane carries the supply rails and can be divided into regions, provided each region is wide enough to carry its current without an excessive drop and each has adequate decoupling. Isolating a noisy rail from a sensitive one is a legitimate reason to divide the plane; subdividing it for convenience is not.
Step 6: Routing Signals and Vias
Route the critical nets first while space is still available: clocks, differential pairs, high-speed buses and any trace with a length or impedance constraint. Keep the return path in mind with every layer change, and add a ground via beside each signal via on a high-speed net so the return current can follow.
Use vias to connect power and ground pins to the inner planes rather than creating a network of wide traces on the outer layers. For decoupling capacitors, keep the via and trace from the pad to the plane as short as possible, because that inductance is what limits the capacitor at high frequency.
Avoid acute angles in routed copper and unnecessary layer changes. Each via adds inductance and a discontinuity, and the accumulation of small discontinuities is what turns a working prototype into a board that fails EMC testing.
Step 7: Design Rule Check and Simulation
Run the full design rule check and treat it as a gate rather than a formality. Clearance violations, unconnected nets, overlapping mask openings and silkscreen over pads are all cheaper to fix now. Set the rules from the fabricator’s capability sheet rather than from the tool’s defaults.
For high-speed interfaces, simulate what matters. A quick impedance check on the critical traces and a look at the return path continuity under each of them will catch most problems. A full electromagnetic simulation is rarely needed on a four-layer board, but a review of the stackup against layer stackup examples is always worth the time.
Step 8: Fabrication Data and Handoff
Export the fabrication package: Gerbers or an ODB++ archive, the drill file, the stackup drawing with impedance requirements, and the netlist for electrical test. Add a readme that states the surface finish, the board thickness and tolerance, and any special requirement such as controlled impedance or a specific material.
Then review the package as a set. Layer counts should agree between the drawing and the Gerber files, the drill file should reference the correct apertures, and the outline should close. Most handoff problems are inconsistencies between documents rather than errors inside them.
For designs with a switching supply, review DC-DC converter layout and routing before release, and check the build against manufacturable PCB design guidelines so the first prototype is also a producible board.
FAQ
Is four layers enough for high-speed signals? It is enough for most interfaces when the stackup is planned and the return paths are continuous. The limit is usually routing density rather than electrical performance, and a design that runs out of routing space is a candidate for six layers rather than for a faster laminate.
Should the power plane be on layer 2 or layer 3? Either works, but the ground plane should sit adjacent to the layer with the fastest signals. Keeping the ground plane next to the critical routing layer gives those traces the tightest return path.
Do I need a ground plane under every trace? Every high-speed trace needs a reference, and the ground plane should be continuous beneath the critical nets. Low-speed control signals tolerate more flexibility, and understanding prototype requirements for multilayer boards helps set that priority before routing begins.
