High Frequency HDI Stackup Design Rules
As soon as a design needs more connections per square centimetre than through vias will allow, the stackup becomes a high density interconnect problem. The transition is not gradual: at a certain density the escape routing from a large array package simply cannot be completed on the available layers, and the only way forward is to add microvias, thinner dielectric and more layers in a build-up structure.
An HDI stackup that performs at high frequency is the result of a small number of decisions made early: the number of build-up layers, the symmetry of the structure, the position of the reference planes, and the way microvias are stacked and filled. This article sets out those decisions and the reasoning behind them.
What HDI Actually Changes
A conventional multilayer board connects every layer with a drilled hole that passes through the whole thickness. An HDI board uses laser drilled microvias that connect only the layers they need to connect, with a typical diameter of a tenth of a millimetre and a depth no more than about one to one with the diameter. Removing the through via frees the space it occupied on every other layer.
The freed space is what allows dense escape routing, but the holes themselves are not free. A microvia that connects more than one layer pair is a stacked via, and stacked structures concentrate thermal expansion and plating stress in the same vertical column. That is why the build sequence, and not only the finished cross section, has to be considered during design.
Symmetry And Board Warpage
HDI cores are laminated more than once, and every lamination cycle applies heat and pressure to an asymmetric structure if the designer allows one. Copper distribution, dielectric thickness and the position of the neutral axis all influence how much the finished board bows. A board that warps by more than the assembly equipment tolerates cannot be placed and reflowed reliably, regardless of how good the routing is.
The practical rule is to mirror the structure about the centre line. If layer two is a signal layer over a ground plane, the corresponding layer near the bottom should be a signal layer over a ground plane as well, with matching copper thickness and dielectric thickness. Deliberate asymmetry is sometimes unavoidable, and when it is, the bow should be predicted rather than discovered.
Reference Planes And Impedance Control
Microstrip and stripline geometries depend on a solid reference plane at a defined distance. In HDI, thin dielectrics make the impedance very sensitive to that distance, so a plane that is broken by a clearance for a via or a split for a different supply will change the impedance of anything routed over the gap. Every signal layer needs its own continuous reference, and the thickness between them must be controlled to a tight tolerance rather than a nominal value.
Differential pairs add a second constraint, because the two traces must share the same reference and see the same environment along their length. Routing one member of a pair over a plane and the other over a gap is a common layout error in dense boards, and it shows up as a rise in common mode conversion rather than as a classic impedance mismatch.
Microvia Geometry And Reliability
A microvia is plated in the same way as any other hole, and the same failure modes apply with less margin. Resin recession at the bottom of the via, incomplete fill before copper plating, and separation between the via wall and the target pad are all routine concerns. Where the via must be filled, the choice between copper filled vias and resin plugged and capped vias changes both the cost and the reliability of the structure.
The reliability question is how the via responds to thermal cycling. A via stacked directly on another via concentrates strain, while a staggered structure distributes it. Where the design allows, staggering costs nothing and improves life substantially. Where the density does not allow it, the via stack selection should be made with the thermal cycle counts of the product in hand rather than by default.
Materials And Layer Assignment
High frequency HDI usually means a low loss laminate, which in turn means a different dielectric constant and a different coefficient of expansion from the standard FR-4 used for the core. Mixing materials in one stackup is normal, and it means the layer assignment has to keep the low loss material where the high speed signals actually run rather than spreading it evenly.
Where dense fine pitch devices sit on the outer layers, via in pad may be required, and the choice between via in pad and a plated through hole determines whether the assembly process needs filled and capped vias. That decision reaches back into the stackup, because filling a via requires a minimum dielectric thickness above it.
Thin dielectrics also change the way the board behaves electrically in ways that are easy to forget. Because the signal layer sits only a few tens of micrometres above its reference, the trace becomes narrow for a given impedance, which raises conductor loss even as the thin, low loss dielectric reduces it. The two effects partly cancel, and the balance is what the loss budget has to be built on rather than on the laminate datasheet alone.
Checks Before Releasing The Stackup
Several checks catch most HDI problems before fabrication. Count the lamination cycles and confirm that every microvia spans no more than one dielectric layer in a single cycle. Verify that the aspect ratio of each via is within the fabricator’s capability, and that the drill to copper distance at the target pad is achievable with the registration tolerance quoted. Check that the impedance targets are stated with a tolerance and a layer, not as a single number for the whole board.
Finally, confirm the panel construction. HDI panels are made on thin cores and laminated in multiples, and the number of build-up steps drives yield, lead time and cost more than any other single decision. A stackup that meets all the electrical requirements but needs one more lamination cycle than the fabricator can do reliably is not a manufacturable stackup.
A final check concerns testability. Dense HDI boards leave little room for probe pads, and the test points that remain must not sit on a microvia or disturb a controlled impedance trace. Planning the test access at the same time as the stackup avoids the situation where a finished design cannot be tested without removing the ground plane under a probe pad.
FAQ
How many build-up layers are usually enough? Most designs are solved with one or two build-up layers per side. Each additional layer adds a lamination cycle, so the target is the smallest number that completes the escape routing with acceptable via geometry, not the largest the fabricator can make.
Can microvias be placed directly on a pad? They can, but the pad must be a via in pad design that is filled and capped so the surface is planar for paste printing. An unfilled microvia in a solder pad wicks paste away during reflow and produces voids and open joints.
Is HDI always necessary for high speed? No. Below roughly ten gigabits per second a standard multilayer board with a good stackup and controlled impedance will usually meet the loss and skew budget. HDI is driven by density and by the escape routing of fine pitch devices as much as by data rate.
