High-Speed PCB Design for Embedded Application Processors
Application processors that pair a high-performance cluster with an efficiency cluster concentrate a large amount of switching activity into a small package. The board around them has to deliver several amperes of transient current, carry multi-gigabit differential pairs, and keep high-speed PCB design practice consistent from the processor escape all the way to the far end of the memory bus. Boards in this class rarely fail because a single rule was broken. They fail because several marginal decisions add up, and the symptom usually appears only under full load or during certification.
What Makes This Class of Processor Different
An application processor that integrates two compute clusters, a graphics unit, a display pipeline and several serial interfaces presents a design problem that is mostly about current and return paths. The nets with the fastest edges are often not the ones that cause trouble first. The transient current drawn when the device changes power state is a more common source of intermittent failures. A layout that satisfies the rules for the differential pairs but ignores the impedance of the core supply will produce a board that boots cleanly and then resets under load. It helps to treat the device as three separate problems: a power delivery problem, a memory interface problem, and an interface escape problem.
Reference Planes and Layer Stackup
The layer next to the processor side of the board carries most of the return current, so it should be a solid ground plane with no routing slots beneath the device. If the processor is mounted on the top layer, layer two must be an uninterrupted ground plane, and the same is true on the bottom side. Splitting that plane to route a few signals saves a layer and costs far more later, because every split forces return current to detour and increases the loop area of the fastest nets. A typical eight-layer stack for this class of board uses two signal layers, ground, signal, power, ground, and two more signal layers, keeping the power plane adjacent to a ground plane so the plane pair still provides useful decoupling above a few hundred megahertz. The counting rules behind that arrangement are described in this article on layer stackup from one to eight layers.
Power Tree Analysis and Copper Capacity
Before routing begins, draw the power tree and record the current of every rail, the source of each rail, and the order in which the rails come up. Copper width should then be calculated rather than estimated, because power integrity at the device depends on the impedance of the entire path and not on the width of any single segment. A working figure for inner layers at moderate temperature rise is about 1 mm of copper per ampere, but the number that matters is the width of the narrowest point in the path, not the average width. Vias restrict that path. A rail that crosses a plane through a single via is limited by that via, so power transitions should use a cluster of vias large enough for the current and arranged so the current spreads across the plane. The regulator should sit close enough that the high-current loop between its input capacitor, its switch node and its ground return stays small. The layout guidance in this article on DC-DC converter layout and routing applies directly to the rails that feed the processor cores.
Decoupling Capacitor Placement and Via Count
Decoupling works only when current flows through the capacitor before it enters the pin. That means the capacitor body sits between the plane and the pin, the trace from the pad to the pin is as short as the placement allows, and the ground connection returns to the plane without a long detour. A useful convention for this class of device is two ground vias per ground pad for capacitors of 10 uF and above, and one via per pad for smaller values, with the vias placed against the pad rather than at the end of a stub. Drilling and annular ring limits constrain how many vias will fit, and the trade-offs are the same ones that govern via selection for any dense ball-grid escape. Capacitors that share a plane with a switching regulator should be grouped by rail, not scattered across the device footprint.
DDR Routing: Impedance, Reference and Escape
All memory signals are controlled-impedance traces. Single-ended nets are usually designed for 50 ohms and differential pairs for 100 ohms, both within about ten percent. The layer beneath the memory devices must be a complete ground plane, because a return path interrupted by a row of vias turns a matched trace into a stub with a resonance of its own. Route byte lanes together, match length within each lane rather than across the whole bus, and keep the timing skew between the clock and its associated lanes under control. Memory should sit close to the processor and away from board edges and metal connectors, since a discharge event coupled into a long unterminated net is a common cause of a device that locks up in the field but passes bench testing. The general method is described in this article on high-frequency traces and data bus routing.
PCIe and MIPI Interface Routing
Serial interfaces have their own constraints. Lane order between a processor and a connector may be swapped as long as the polarity inside each pair is preserved, which makes escape routing much easier on a dense ball grid. AC coupling capacitors belong near the connector rather than near the processor, and the smallest package that meets the voltage rating reduces the impedance discontinuity in the pair. Route the pairs side by side with no other traces or vias between them, and add ground stitching only where the pair changes reference planes. Camera and display interfaces should run on inner layers with a continuous reference plane, because routing them on the surface invites radiation from the pair and coupling into nearby analog nets.
ESD Protection at Connectors and Board Edges
ESD protection depends more on geometry than on component selection. Connectors should be recessed into the enclosure wherever the mechanical design allows, so a discharge has to travel further before it reaches circuitry. Keep-out zones around sensitive signals, and generous separation between shield pins and signal pins, reduce the energy that couples into the board. The protection device must be closer to the connector than to the integrated circuit, with the topology connector, then clamp, then circuit, so that the transient is attenuated before it reaches the pin. The ground via for a clamp should be placed immediately beside its ground pad. A large, unbroken surface ground on the connector side of the board does more for ESD protection than an extra pair of layers, and this is one place where a cheap change in the stackup is worth more than an expensive one.
Thermal Path Through the Ball Grid
Heat leaves a processor through the ball grid, the copper it is soldered to, and the vias that connect that copper to the inner planes. Copper directly under the device should be connected in a mesh pattern that links adjacent power and ground balls, with enough vias to move heat into the inner layers without cutting the plane into fragments. Spreading copper out from beneath the ball grid to the surrounding board area is usually more effective than adding layers. Thermal vias should be capped or plugged if they also carry solder, and their count should be based on the power dissipation rather than on the available space.
Design Review Before Release
A board of this complexity should not go to fabrication without a second pass over the items that are invisible on a screen: plane continuity under every high-speed net, current capacity at every via transition, capacitor placement on the rails that switch hardest, and clamp placement at every connector. At gopcb these checks are part of the standard review for processor boards, because each of them costs a respin when it is missed and almost nothing when it is caught.
FAQ
Does the processor always need a ground plane on layer two? Yes, if the device is mounted on the top layer. That plane is the return path for the fastest nets and the primary spreader for heat, and routing through it degrades both at once.
How many vias should a power rail have at a plane transition? Enough that the via cluster carries the rail current at the same temperature rise as the copper trace, which in practice means several vias for anything above about one ampere.
Can a serial lane pair be reordered between the processor and the connector? The lane order can be changed to simplify escape routing, but the positive and negative conductors inside one pair must never be swapped.
