IC Substrate PCB: Build-up Layers and Fine Line Technology

An IC substrate sits between a bare die and the board it is mounted on, and it is closer to a semiconductor product than to a printed circuit. Its conductors are measured in single-digit micrometres, its vias are formed by laser, and its materials are chosen for electrical and mechanical behaviour at a level of precision that ordinary circuit boards never approach. Understanding why it is built the way it is explains most of what makes it difficult and expensive.

What an IC Substrate Does

The substrate performs three jobs at once. It fans the fine pitch of the die out to a pitch that the main board can accept, it delivers power to the die with very low impedance, and it carries away the heat that the die produces. On a large processor the power delivery network may include hundreds of capacitors and several copper planes, and the thermal path may run through a lid into a heat sink.

The package type follows from the application. Wire bonded substrates are used where the pin count and the frequency are moderate, flip chip substrates where the die has thousands of connections and the electrical path must be short, and chip scale substrates where the package must be almost the size of the die itself. Each of them places different demands on the same underlying technology.

Why the Lines Are So Small

The escape routing of a flip chip die begins at a pad pitch of a hundred micrometres or less, and every signal has to get out of that array before it can be routed anywhere else. If the substrate could not form lines and spaces far finer than a conventional board, the fanout would require more layers than the package can accommodate in its thickness budget.

So the line width and spacing fall from the seventy five micrometres typical of advanced circuit boards to fifteen, ten and sometimes below eight. That is not a matter of better etch control alone; it requires a different way of making the conductor, because subtractive etching cannot hold that geometry on a copper layer of useful thickness.

Build-up Construction

An IC substrate is built from a core with build-up layers added on one or both faces. Each build-up layer consists of a thin dielectric film, a laser drilled via and a plated conductor pattern, and the layers are added sequentially so that each new layer can be drilled and plated without disturbing the ones below. The count runs from two or three build-up layers on a modest device to eight or more on a large processor substrate.

Coreless constructions remove the traditional core entirely and build the stack from the build-up films alone. They allow finer vias and thinner packages, and they are used for the most demanding mobile and high performance parts. The trade is mechanical stiffness: without a core the substrate is more flexible, which changes how it behaves during assembly and under the thermal load of the die. The general principles of layer arrangement are described in layer stackup for one to eight layers.

The SAP Process

The conductors are formed by a semi additive process. A thin seed layer is deposited on the dielectric, a resist is patterned over it, and copper is plated into the openings. The resist and the seed are then removed, leaving the conductor standing on the surface rather than being etched down from a full copper sheet. Because the geometry is defined by plating into a resist rather than by etching sideways, much finer features are possible with a predictable cross section.

A modified version of the same process, in which the seed layer is etched back after plating, is used where the finest lines are required. Both depend on the plating chemistry and on the current distribution across a panel that is often very large relative to the feature size. The way additives control the deposit is described in electroplating additives.

Laser Microvias

Vias in a build-up layer are formed by laser, with diameters commonly between thirty and seventy five micrometres. The laser removes the dielectric down to the copper below, which stops the process and provides a natural depth limit. The via is then plated, and where the next layer must be built on top of it, it is filled with copper and planarised so that the following laser via lands on solid metal rather than on a void.

Stacked microvias are essential for the density of a modern processor substrate but they concentrate stress in a small volume, and the reliability of the structure depends on the fill quality beneath each level. This is one reason the process window is narrow and the inspection regime is heavy. The filling process is described in electroplating and via filling in HDI.

Materials

The dielectric for the build-up layers is normally a film material rather than a glass reinforced laminate, because the film can be applied thinly and uniformly and can be laser drilled with a clean profile. The better known of these films is an epoxy based build-up material used for high performance processors, while a bismaleimide triazine resin is used where cost and process maturity matter more than the lowest possible loss.

The copper is very thin by circuit board standards, often under twelve micrometres in the build-up layers, which is what makes fine line plating practical. The choice of material also affects the thermal expansion of the finished substrate, because the die and the substrate must expand at similar rates or the solder joints between them will be stressed with every power cycle.

Design Features That Matter

Placing vias inside pads is normal on a substrate, because there is no room to do anything else. That means the via must be filled and capped flat enough for the die attach or for a solder ball, and the flatness requirement is far tighter than on an ordinary board. The same feature appears in the power delivery network, where via arrays carry current between planes.

Impedance control is applied to the high speed interfaces, with tolerances that are tighter than on a circuit board because the losses and reflections that matter at these data rates are small. Thermal structures are also part of the layout: copper planes, thermal via arrays and a balanced copper distribution that keeps the substrate flat through repeated lamination. The comparison with conventional via options is set out in via in pad or plated through.

Yield and Verification

Yield falls steeply as the geometry shrinks. A defect that would be a minor cosmetic issue on a circuit board is a fatal open or short on a substrate with ten micrometre lines, and the inspection has to find it across a panel that may hold hundreds of units. Optical inspection, electrical test of the finished substrate and sampling by microsection are all used, and the test coverage is part of what the customer pays for.

Reliability verification includes thermal cycling of the assembled package, which is the test that exposes poor via fill and mismatched expansion, and high temperature storage. Because the substrate is inside the package, a failure here cannot be repaired, so the qualification is performed on the design and on the process rather than on individual units.

FAQ

Is an IC substrate a PCB? It is made with related processes but with far tighter geometry and different materials. It is properly a semiconductor packaging component rather than a circuit board.

Why is a coreless substrate used? To allow finer vias and a thinner package. The trade is lower mechanical stiffness, which has to be managed in assembly and in service.

Why is the semi additive process necessary? Subtractive etching cannot hold lines and spaces of ten micrometres on a useful copper thickness, because the etchant removes material sideways as well as downwards.