Impedance Design on a Six-Layer Stack-Up
A six-layer board is the point at which controlled impedance stops being optional and starts being structural. There are enough layers to give fast signals a proper reference, and enough density that the trace geometry which produces a given impedance has to be designed rather than discovered. The decisions that matter are taken in the stack-up, and everything afterwards follows from them.
Where the Six-Layer Stack-Up Decides
Two arrangements dominate, and they suit different kinds of design.
The first places signal layers next to ground planes and pairs the power layer with a ground layer: signal, ground, signal, power, ground, signal. Every signal layer has an adjacent plane, including the outer layers, which gives each trace a continuous reference and a short return path. It suits dense designs that need the routing capacity.
The second puts the planes on the outside and the signal layers inside: ground, signal, ground, power, signal, ground. Here the outer layers of the board are essentially plane copper, which shields the inner routing from the environment and from each other, and the signals are routed between references on both sides. It is used where the component density is lower and the routing is less demanding.
In both cases one detail matters more than the rest: the spacing between the power plane and the ground plane it is paired with. Keeping those two planes close together increases the capacitance distributed between them, which lowers the impedance of the supply at the frequencies where the discrete capacitors have stopped responding. It also means the dielectric between them is thin, which has consequences for the impedance of any signal reference to either plane.
What Determines the Impedance
The characteristic impedance of a trace is set by five things, and on a six-layer board there is limited freedom to adjust most of them individually.
Trace width has the largest effect for a given construction: a wider trace lowers the impedance, and a narrower one raises it. Spacing to a neighbouring trace matters where the geometry is close enough for the two to couple. The dielectric thickness between the trace and its reference plane raises the impedance as it increases, which makes it the parameter that ties impedance to the stack-up. The copper thickness and the thickness of the solder mask over the trace lower the impedance slightly, and the dielectric constant of the material lowers it as it rises.
The interaction is why a stack-up change is never local. Thinning the dielectric to reduce crosstalk also lowers the impedance of every trace above it, so the widths have to be recalculated; and adjusting the widths to restore the impedance changes the spacing the design was using for isolation.
The Practical Sequence
The order that avoids iteration is to fix the electrical requirements first, then the construction, then the geometry.
Start with what the interfaces need: which nets require a controlled impedance, what value they require, and how much tolerance the design can absorb. Then choose a construction that supports those values with trace widths the routing can accommodate. Only then calculate the widths, and check that the resulting widths and spacings are consistent with the density of the design and with the fabricator’s minimum features.
Where the calculation shows a conflict, the resolution is usually in the construction rather than in the geometry: a different dielectric thickness, a different material, or a different assignment of which layers carry the controlled-impedance nets.
Calculating with Real Numbers
An impedance calculation is only as good as its inputs, and three of them are commonly wrong.
The dielectric constant should be the value for the material and construction being used, not a generic figure for the laminate family. Filled and high-performance laminates have values that differ from plain FR-4, and the value also varies with frequency. Using the manufacturer’s data for the actual material removes a systematic error.
The dielectric thickness is not the spacing between layers in the drawing; it is the thickness of the dielectric above the trace after lamination, which depends on the prepreg and its resin content. Building the model from the fabricator’s own stack-up rather than from an idealised one keeps the two consistent.
The third input is the soldermask, which is often neglected. A coating over a trace changes the effective permittivity around it and lowers the impedance slightly, and on narrow traces at high rates the effect is large enough to matter. A model that excludes it will predict a higher impedance than the board delivers.
A field solver is the normal tool for the calculation, since the closed-form approximations assume geometries that fine traces on thin dielectrics no longer satisfy. The value to confirm at the end is whether the result meets the requirement with margin for the fabrication tolerance, not whether it equals the target exactly.
Verifying on the Panel
An impedance coupon is the standard method of confirmation. The coupon is a set of test structures built into the panel using the same layer, the same construction and the same trace geometry as the product, and it is measured after fabrication.
Two details make the coupon useful rather than decorative. It has to be built from the same geometry as the traces it is verifying, which means the design has to state that geometry explicitly in the fabrication data rather than leaving the fabricator to infer it. And the tolerance on the coupon measurement has to be agreed in advance, since the coupon is only meaningful if a result outside the tolerance triggers a correction.
Because the measurement happens after the panel is built, the coupon is a control rather than a design tool. Its value is that it closes the loop: it shows whether the model, the material and the process agreed, and it provides the evidence that a fabricator can hold the impedance a design requires before that design goes into volume.
<img src="https://www.gopcba.com/wp-content/uploads/2026/05/太阳能监控摄像头PCBA.png" alt="impedance coupon structures on a panel edge” />
Mistakes That Repeat
A few errors appear often enough to be worth listing. Changing the stack-up for manufacturing convenience without recalculating the impedances is the most costly, because the change looks harmless and invalidates every controlled trace on the board. Copying geometry from a previous design without checking that the construction is the same is the most common, since the numbers look familiar and the dielectric beneath them is not. And specifying a tolerance without a measurement method leaves the requirement unverifiable, which in practice means it is not met.
Where the impedance requirement exists but the design has no coupon, the number on the drawing is a request rather than a specification. The process of specifying, verifying and testing controlled impedance is set out in our guide to impedance control, the layer arrangements that support it are described in the article on layer assignment, and the measurement itself is covered in the note on impedance testing.
FAQ
Which six-layer arrangement is better? The one whose plane positions match the signals the design has to route. Both are sound; the choice follows from whether the design needs the outer layers for routing or for shielding.
Why does a stack-up change break the impedance? Because impedance depends on the dielectric thickness and permittivity beneath each trace. Changing the construction changes those values for every trace on the affected layers.
Can the impedance be verified after the boards are made? Yes, through a coupon built with the same geometry. Without one, the requirement cannot be confirmed and the delivered boards have to be taken on trust.
