Why 50 Ohm Impedance Is Hard To Hold

Ask a fabricator to hold fifty ohms and the answer will be a tolerance, not a number. That is honest, because the impedance of a trace on a real board is the product of four variables, each with its own process window, and the final value is the sum of their deviations rather than any one of them. A design that quotes a target without a tolerance and a reference layer has not specified anything a factory can act on.

This article explains where the fifty ohm convention comes from, which variables actually move the impedance, and what a fabricator can and cannot control. The aim is to make the 50 ohm impedance requirement in a fabrication drawing mean something a factory can act on.

Where The Convention Comes From

Fifty ohm impedance is not a law of nature. It is a compromise chosen by the RF industry and inherited by digital design, sitting between the lowest loss point, which is higher, and the highest power handling point, which is lower. The test equipment, connectors, cables and instruments in a laboratory are all built around that ecosystem, so a board designed to a different value would need matching networks at every interface.

Once the choice is made, the real question becomes how tightly the value must be held. A single ended 50 ohm impedance trace in a controlled environment is easy. The difficulty appears when the requirement has to hold across a panel, across a production run, and across the copper geometry variations that the etching process inevitably introduces.

The Four Variables And Their Windows

Characteristic impedance rises with dielectric thickness and falls with trace width, dielectric constant and copper thickness. The designer sets the target and the fabricator holds the geometry. Inner layer trace widths are usually held to within about half a thousandth of an inch after etching, outer layers are less predictable because of plating thickness variation, and dielectric thickness is normally quoted at plus or minus ten percent.

Multiplying those windows together gives the impedance window. Inner layers are typically held to plus or minus seven percent and outer layers to plus or minus ten percent, and a request for five percent on an outer layer usually triggers an engineering review rather than an automatic acceptance. The tighter inner layer figure is not a statement that inner layers are easier; it is a recognition that once the press cycle is complete, the dielectric thickness can no longer be adjusted.

Etching, Trapezoids And The Profile

Etching does not produce a rectangular cross section. It attacks the top of the trace for longer than the bottom, so the conductor becomes a trapezoid whose average width differs from the width drawn in the layout tool. The etch factor, the ratio of the width lost per side to the depth of copper, decides how much narrower the finished trace is than the artwork.

This is why the same artwork can produce different impedances on a one ounce and a two ounce copper layer, and why the fabricator compensates the artwork before imaging. If the design file is quoted as if the artwork width were the finished width, the measured impedance will come back low every time, and the correction will be applied by the factory without the designer knowing.

Dielectric Thickness And Prepreg Flow

The distance from the trace to the reference plane is the most powerful variable in the equation and the hardest to hold. Prepreg flows during lamination, filling the space around the copper features, so the dielectric thickness over a dense copper area is different from the thickness over an open area on the same layer. A board with a large power plane on the layer below will show lower impedance over that plane than over a sparsely populated region.

Choosing the right prepreg construction and controlling the resin content is how a fabricator manages this, which is why the stackup drawing should specify the construction rather than only the finished thickness. Where several prepreg plies of the same type are used, the flow behaviour is more predictable than where a single thick ply is stretched to do the job.

Glass Weave And Local Dielectric Constant

Woven glass fabric has a dielectric constant different from the resin that surrounds it. A trace that happens to run directly over a bundle of glass yarns sees a higher effective dielectric constant than a trace running over the resin rich window beside them. The result is a periodic variation in impedance along a single trace, at the pitch of the weave.

The effect is small at low frequency and significant at high frequency, and it is worst where the weave pitch is comparable to the trace width. Spread or mechanically spread glass, and in some cases a rotated fabric orientation, reduce it. Differential pairs suffer more than single ended traces because the two members of a pair can straddle a bundle differently, converting part of the differential signal into common mode.

Solder Mask And The Surface Finish

The coating over a trace changes the effective dielectric constant of the medium above it, so the impedance of a finished board is lower than the impedance predicted before coating. The shift depends on the mask thickness and on how much of the field is in the air above the trace, which is why narrow top layer traces shift more than wide ones.

This impedance drop after solder mask is normally absorbed by designing to a slightly high value before coating, but the assumption has to be stated. Where the geometry is marginal, the fabricator can measure a coupon rather than relying on the model, and the manufacturing tolerance carried by the finished board is what the test coupon actually reports.

Writing A Requirement The Factory Can Meet

A usable impedance specification names the target, the tolerance, the reference layer, the layer on which the trace runs, and the test method. It identifies the specific nets or net classes to which the requirement applies rather than applying it to the whole board, and it accepts that a coupon measurement is the evidence of compliance.

Designing the geometry to a microstrip or stripline model and then asking for a value that the process cannot hold is the most common source of impedance disputes. Running a field solver on the actual stackup, with the dimensions the fabricator quotes rather than the ones the design intended, takes an hour and prevents a prototype respin.

FAQ

Why does the measured impedance differ between boards of the same design? Because the variables differ. Dielectric thickness, etched width and copper thickness all vary within their process windows, and the boards that land at opposite ends of those windows report different impedances even though every step was in specification.

Should the whole board be controlled to fifty ohms? No. Only the nets that need it should carry the requirement, which keeps the fabrication cost and the yield impact confined. Marking every net as controlled impedance adds cost without adding performance.

Can impedance be fixed after fabrication? Not on an inner layer, and only marginally on an outer layer. Placing a compensation pad or adjusting the mask thickness are the only levers, and both are small. If the value is critical, the correction belongs in the stackup before the first panel is laminated.