Heavy Copper in HDI Boards: Compatibility and Design Rules

Two directions in board technology pull against each other. High density interconnect pushes toward thin dielectrics, small vias and fine traces, because that is how more connections fit into less area. Heavy copper pushes toward thick conductors and wider features, because that is how large currents are carried and heat is moved away. Devices that need both — a charging module, a high-power converter with a dense control section, an automotive power stage with a fine-pitch controller — force the two into the same stack, and that combination is not a matter of adding copper to an HDI design.

What Each Side Brings

HDI board construction delivers density: microvias, blind and buried vias, fine line widths and small pads, which together allow a large number of connections in a small area with short paths.

Heavy copper describes conductors well beyond the usual foil thickness, from a couple of ounces per square foot upward to values several times that. The benefit is straightforward: a thicker conductor has a larger cross-section, so for a given trace width it carries more current with less resistive heating and spreads heat more effectively.

The electrical gain is not linear in thickness for every property, but for resistance and for current capacity the relationship is direct: doubling the copper section halves the resistive loss at the same current, or allows a narrower trace for the same loss. What does not scale so conveniently is everything else — etching, lamination, drilling and reliability.

Choosing the Copper Weight

The starting point is the current the trace has to carry, the temperature rise that can be tolerated and the width the layout can afford. Those three determine the copper weight, and the answer is usually expressed as a compromise because the widest traces the current demands are also the ones that consume the most routing area.

What makes HDI different is the interaction with everything else in the stack. A thicker copper layer makes the finished board thicker for the same number of layers, and if the overall thickness is constrained the layer count has to fall — which is at odds with the density the HDI side of the design needs. Thick copper also makes the pressed stack less uniform, because the copper features leave voids that resin has to fill and the resin has to fill them consistently across a panel that is not flat to begin with.

Etching and the Real Limits on Width

Heavy copper does not etch the way thin foil does. The etchant attacks the sides of the trace as well as the exposed surface, and on a thick layer the sideways removal is a large fraction of the thickness. Traces come out narrower than drawn, and the effect is not uniform: features in dense areas etch differently from isolated ones, because the local chemistry is different.

The practical response is to design to wider minimum features and to compensate the artwork. The usable minimum width and spacing rise with copper thickness, roughly in proportion: a two-ounce layer might allow a few tenths of a millimetre, a four-ounce layer needs noticeably more, and the figure should come from the fabricator rather than from the design rule default in the tooling.

Where the design is dense, the compensation technique is to add material in the artwork where the etch is expected to remove it, keeping the finished geometry on target. This is why thick-copper boards are quoted with their own minimum features rather than with the general capability of the fabricator.

Thermal Design

Heavy copper pays back twice: it reduces the heat generated by conduction losses and it moves the heat away from the device that generates it.

The structure that does the second job is a copper area beneath the power device, connected through the board to the other side, where it can reach a heatsink or spread into open copper. The connections are thermal vias — clusters of small plated holes that carry heat as well as current — and their effectiveness depends on how well they are plated and how the copper they join is arranged. A large area of copper on the outer layer is of limited use if the path beneath the device is a handful of poorly plated vias with a narrow landing area on the far side.

The design work is therefore a thermal path, not merely a copper pour. The considerations are similar to those in the article on heavy copper PCB manufacturing: the copper is a manufactured feature with its own process limits, and treating it as a drawing instruction rather than a process decision is how designs end up either over-thick or under-sized.

Via Design Under Thick Copper

Vias change in two ways when the copper is thick.

Mechanically, a hole through thick copper is harder to drill cleanly, and the plating that lines it has to be thicker to be reliable. The usual approach is to increase the hole diameter rather than push the process, since the copper in the barrel needs a reasonable aspect ratio to plate consistently. Design rules for ordinary boards assume the barrel can be small; a thick-copper design has to allow more.

The second change concerns the vias that carry current rather than signals. A single large via is not always the best answer; several smaller vias distribute current and heat more evenly and are easier to fill and plate. Where the design is also an HDI board, the microvias used for signal escapes sit alongside these larger structures, and the two sets have entirely different rules, which is why the design rules have to distinguish between them rather than applying one set to all vias.

Base Material and Reliability

Thick copper imposes mechanical stress on the stack, and the material has to tolerate it. High glass transition temperature laminates are usual on these boards, because the pressing and the operating temperatures both push the resin toward the point where it softens.

The expansion behaviour matters for the same reason. Copper and laminate expand at different rates, and the difference between a thick copper layer and the dielectric beside it produces stress at every temperature change — during manufacture, during assembly and in service. A design that is electrically correct can still fail at a via barrel or at the interface between layers if that mismatch is not accounted for, which is why reliability testing on these boards includes thermal cycling rather than only electrical measurement.

Signal Integrity in the Same Stack

The thick copper layers that carry power also sit next to the fine traces that carry signals, and the combination changes the environment for those signals.

A thick conductor layer is not a good place for impedance-controlled traces, because the geometry that produces a controlled impedance is difficult to hold when the conductor thickness is comparable to the dielectric height. In practice the design separates the two functions: high-speed signals live on layers whose stack-up was designed for them, and the heavy copper layers carry power and are used as reference planes where they are solid.

Ground planes formed by thick copper are electrically beneficial, since they present low impedance and stiffen the board. The requirement is continuity: a plane interrupted by the clearances that thick-copper etching demands can behave as a split plane, and a signal crossing it loses its return path. Keeping the high-speed routing over the continuous parts of the plane, and providing stitching where the plane is unavoidably interrupted, is the same discipline used on any other board — with less margin, because the break in the plane is wider.

A Representative Approach

A charging module illustrates the compromise. The current path needs a conductor weight in the low ounces, and the same board carries a controller and its support circuitry at ordinary density with an HDI escape for the fine-pitch parts.

The design that works typically does the following: chooses the copper weight from the current requirement with a defined temperature rise rather than from habit; widens the minimum feature sizes on the heavy layers to match what the fabricator can etch after compensation; places a solid copper area under each power device with a cluster of plated vias through to the opposite side and a large landing area there; uses through-hole diameters sized for reliable plating rather than for density on those current-carrying vias; selects a high transition temperature laminate; keeps the controlled-impedance routing on layers designed for it; and verifies the thermal path by simulation rather than by assuming the copper area is enough.

The Decision to Combine Them

Combining HDI and heavy copper is worth doing when a single product genuinely needs both dense logic and high current, because it avoids splitting the design across two boards and the connectors and interfaces that would follow. It costs more per unit area, it takes longer to design and it narrows the set of fabricators who can build it.

Where the current requirement is modest or the signal density is low, the sensible move is to solve the dominant problem with a conventional stack and not pay for the combination. Where both are genuinely present, the design has to be treated as one problem rather than as two halves joined at a boundary.

The design questions that arise in the dense half of such a board are the ones covered in the article on HDI board design with blind and buried vias, and the review that catches conflicts between the two halves is set out in the layout quality checklist.

FAQ

Can heavy copper and fine traces exist on the same layer? Not usefully. Etching that produces wide features cannot hold fine ones, so the design separates the two onto different layers and accepts the extra layers this requires.

Why do thick-copper vias need to be larger? Because the barrel has to be plated reliably through a thicker stack. Increasing the diameter keeps the aspect ratio within what the plating process can fill uniformly.

What limits the copper weight on an HDI board? Usually thickness and lamination rather than current. Thick copper raises the finished thickness, forces compromises in layer count and makes the pressed stack harder to fill evenly.