PCB Tolerance and Dimension Rules for Prototypes
Most disagreements between a designer and a fabricator are not about capability but about default values. The designer assumes a tolerance, the fabricator assumes a different one, and the difference is discovered when a connector does not fit or a panel will not sit flat. Writing the dimensions and the tolerances explicitly into the drawing, and knowing which ones the process can actually hold, removes that class of problem entirely.
Defining the Outline in the File
Every design element that matters has to be described in the drawing, starting with the outline. The board shape is normally carried on a mechanical layer, and a keep-out layer can be used in parallel, but the two have different jobs: the keep-out layer prohibits routing and does not define an opening, while the mechanical layer defines the finished shape. When both appear in one file, they should agree, because two disagreeing contours leave the fabricator to guess.
Slots and cut-outs follow the same rule. They are drawn on the mechanical layer as the shape they will be, and the fabrication data is generated from that geometry. A slot whose width is below the smallest router bit cannot be produced, so it has to be widened in the design or removed; the practical floor is around 0.8 mm in most shops.
Dimension Tolerance and Flatness
The outline must match the drawing, and when the drawing does not specify a tolerance, a default of plus or minus 0.2 mm is the usual assumption. That number matters for enclosures, connectors, and mounting holes, because several of them in the same direction can accumulate. Where a dimension is critical, it should be called out individually rather than left to the default.
Flatness is the second geometric requirement. Warpage is usually specified as a percentage of the diagonal, and 0.7 percent is a common limit for a rigid board. It matters because a board that bows will not sit flat on a heatsink or in a fixture, and it also makes fine-pitch placement harder. The causes are usually asymmetric copper distribution and an unbalanced stack, which is why the recommendation to fill large copper areas and to balance the layers belongs to the same discussion; related behavior is described in PCB dimensional stability and expansion.
Layer Orientation Conventions
For a single-sided board, the signal layer is drawn on the top layer when the artwork represents the viewed side, and on the bottom layer when it represents the opposite side. For a double-sided board, the convention is that the top layer is the viewed side with the top legend reading normally, and the bottom layer is the far side with the bottom legend mirrored.
Multilayer stackups add a second convention on top of the first. The lamination order has to be unambiguous, and the source of truth differs between tool generations: newer projects define it in the layer stack manager, older ones may require an explicit note or an external diagram. Where the design files were produced by a tool that stores the order differently, a short note in the fabrication drawing saves a full round of correspondence.
Trace and Pad Compensation
Trace and pad geometry is taken from the drawing, but the fabricator will normally compensate it to suit the process. Pad rings are enlarged where the design allows, particularly on single-sided boards, because a larger pad improves soldering reliability. Where the spacing in the design is tighter than the process can hold, the fabricator will adjust it according to its own pre-production rules, which is a change the designer should know about in advance rather than discover in the finished board.
The finished width of a trace is not the drawn width, because etching removes material from the sides. The usual internal control is plus or minus 20 percent on conductor width, and that variation has to be included in the current-carrying and impedance calculations rather than treated as a rounding error.
Via, Grid and Thermal Pad Rules
Via geometry has recommended values that keep the process comfortable. A via diameter of 0.3 mm or more for the hole and 0.6 mm or more for the pad is a reasonable target, with the component pad at least 50 percent larger than the hole and an aspect ratio no worse than 6:1 for a thin board. Smaller drills exist, since a 0.3 mm tool produces roughly a 0.2 mm finished hole, but yield falls as the aspect ratio rises.
Large copper areas need different treatment. A solid pour over a wide region creates a thermal mass that can bow the board and blister the copper during wave soldering, so the usual recommendation is to lay it as a grid. Grid spacing of at least 10 mil, with 8 mil as the floor, and a line width of at least 10 mil, again with an 8 mil floor, keeps the copper from behaving as one continuous sheet. The trade-offs between grid and solid fill are discussed in copper flooding, mesh or solid.
Where a component pin connects to a large ground or power area, the connection should be made through a thermal pad rather than a solid connection. A cross-shaped relief reduces the heat drawn away from the joint during soldering, which is what prevents the cold joint that a solid connection to a plane tends to produce.
Edge Clearance and Keep-Out
Copper has to stay away from the outline. Inner layer traces and copper should be at least 0.3 mm from the board edge, and outer layer traces and copper at least 0.2 mm, because routing the profile can lift copper that sits closer and take the solder mask with it. Gold finger regions should have no inner layer copper beneath them at all, since exposed copper at an edge is a short waiting to happen; the geometry of slots and edges is covered in PCB slot and edge routing rules.
The keep-out layer exists to enforce this automatically. Where it is used for its proper purpose, prohibiting routing and copper rather than defining an opening, the board edge clearance rules are enforced by the tool instead of by a manual review. That is more reliable than a drawing note, because the rule is applied at every edit rather than once at the end.
Working Numbers to Design To
A short list is worth keeping in mind. Outline tolerance plus or minus 0.2 mm unless specified; flatness 0.7 percent of the diagonal; conductor width tolerance plus or minus 20 percent; minimum spacing 6 mil for a tin-plated finish and 4 mil for a gold finish, adding at least 1.5 mil for every additional half ounce of copper; grid spacing and width 10 mil nominal with 8 mil as the floor; inner layer copper to edge 0.3 mm and outer layer 0.2 mm; minimum slot width 0.8 mm.
These are defaults rather than limits. Every shop has its own window, and the numbers above describe a capable but standard process. The value of writing them down is that a design which stays inside them can be quoted from a catalog and built on a standard line, while a design that pushes one of them moves to a different process with a different price and lead time. Knowing which parameter is being pushed, and why, is what makes the trade deliberate, and it is the difference between a PCB tolerance that was chosen and one that was inherited.
FAQ
What happens if the drawing has no tolerance? The usual default is plus or minus 0.2 mm on the outline. Dimensions that matter should be called out individually so they are not left to that default.
Why lay a large copper area as a grid? To reduce the thermal mass and the stress that a solid sheet puts on the laminate, which otherwise risks bowing and blistering during soldering.
Should a via connect solidly to a ground plane? No. Use a thermal pad. A solid connection draws heat away from the joint and is a common cause of cold solder joints on plane-connected pins.
How close can copper come to the board edge? At least 0.2 mm on outer layers and 0.3 mm on inner layers, so that profile routing does not lift the copper or the mask above it.
